®
X28HC64
64K, 8K x 8 Bit
Data Sheet
June 1, 2005
FN8109.0
5 Volt, Byte Alterable EEPROM
FEATURES
• 70ns access time
• Simple byte and page write
—Single 5V supply
—No external high voltages or V
PP
control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—40mA active current max.
—200µA standby current max.
• Fast write cycle times
—64-byte page write operation
—Byte or page write cycle: 2ms typical
—Complete memory rewrite: 0.25 sec. typical
—Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
—DATA polling
—Toggle bit
• High reliability
—Endurance: 1 million cycles
—Data retention: 100 years
• JEDEC approved byte-wide pin out
DESCRIPTION
The X28HC64 is an 8K x 8 EEPROM, fabricated with
Intersil’s proprietary, high performance, floating gate
CMOS technology. Like all Intersil programmable non-
volatile memories, the X28HC64 is a 5V only device. It
features the JEDEC approved pinto for byte-wide mem-
ories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and
enabling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features DATA Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Intersil’s hardware write protect capability.
Intersil EEPROMs are designed and tested for appli-
cations requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN CONFIGURATIONS
Plastic DIP
Flat Pack
CERDIP
1
2
3
4
5
6
8
9
10
11
12
13
14
28
27
26
25
24
23
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
10
11
12
29
28
27
26
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
I/O
1
12
I/O
0
11
A
1
9
A
3
7
A
5
I/O
2
13
A
0
10
A
2
8
LCC
PLCC
V
CC
WE
A
12
NC
NC
NC
A
7
TSOP
A2
A1
A0
I/O 0
I/O 1
I/O 2
NC
VSS
NC
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A3
A4
A5
A6
A7
A 12
NC
NC
VCC
NC
WE
NC
A8
A9
A 11
OE
SOIC
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
4
3
2
1 32 31 30
X28HC64
7 X28HC64 22
X28HC64
(Top View)
25
24
23
22
13
21
14 15 16 17 18 19 20
I/O
1
I/O
2
I/O
3
I/O
4
V
SS
I/O
5
NC
PGA
I/O
3
15
V
SS
14
I/O
5
17
I/O
4
16
CE
20
I/O
6
18
I/O
7
19
A
10
21
A
11
23
A
8
25
NC
26
X28HC64
A
4
OE
6 (BOTTOM 22
VIEW)
A
12
2
A
7
3
V
CC
28
NC
1
A
9
24
WE
27
5
A
6
4
Bottom View
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC64
PIN DESCRIPTIONS
Addresses (A
0
-A
12
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all
read/write operations. When CE is HIGH, power con-
sumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buff-
ers and is used to initiate read operations.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X28HC64 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC64.
BLOCK DIAGRAM
X Buffers
Latches and
Decoder
A
0
–A
12
Address
Inputs
Y Buffers
Latches
and
Decoder
I/O Buffers
and Latches
65,536-Bit
EEPROM
Array
PIN NAMES
Symbol
A
0
-A
12
I/O
0
-I/O
7
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
CE
OE
WE
V
CC
V
SS
Control
Logic and
Timing
I/O
0
–I/O
7
Data Inputs/Outputs
2
FN8109.0
June 1, 2005
X28HC64
DEVICE OPERATION
Read
Read operations are initiated by both OE and CE
LOW. The read operation is terminated by either CE or
OE returning HIGH. This two line control architecture
eliminates bus contention in a system environment.
The data bus will be in a high impedance state when
either OE or CE is HIGH.
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC64 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 2ms.
Page Write Operation
The page write feature of the X28HC64 allows the
entire memory to be written in 0.25 seconds. Page write
allows two to sixty-four bytes of data to be consecu-
tively written to the X28HC64 prior to the commence-
ment of the internal programming cycle. The host can
fetch data from another device within the system during
a page write operation (change the source address),
but the page address (A
6
through A
12
) for each subse-
quent valid write cycle to the part during this operation
must be the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the
host can write an additional one to sixty-three bytes in
the same manner. Each successive byte load cycle,
started by the WE HIGH to LOW transition, must begin
within 100µs of the falling edge of the preceding WE. If
a subsequent WE HIGH to LOW transition is not
detected within 100µs, the internal automatic program-
ming cycle will commence. There is no page write win-
dow limitation. Effectively the page write window is
infinitely wide, so long as the host continues to access
the device within the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O
7
)
The X28HC64 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC64, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
duce the complement of that data on I/O
7
(i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. Dur-
ing the internal programming cycle I/O
6
will toggle
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
FN8109.0
June 1, 2005
X28HC64
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
WE
Last
Write
CE
OE
V
IH
I/O
7
HIGH Z
V
OL
A
0
–A
12
An
An
An
An
An
An
An
V
OH
X28HC64
Ready
Figure 3. DATA Polling Software Flow
Write Data
DATA Polling can effectively reduce the time for writ-
ing to the X28HC64. The timing diagram in Figure 2
illustrates the sequence of events on the bus. The
software flow diagram in Figure 3 illustrates one
method of implementing the routine.
Writes
Complete?
Yes
Save Last Data
and Address
No
Read Last
Address
IO
7
Compare?
Yes
No
Ready
4
FN8109.0
June 1, 2005
X28HC64
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
WE
Last
Write
CE
OE
I/O
6
V
OH
*
V
OL
HIGH Z
*
X28HC64
Ready
* Beginning and ending state of I/O
6
will vary.
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC64 memories that is fre-
quently updated. Toggle Bit Polling can also provide a
method for status checking in multiprocessor applica-
tions. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow dia-
gram in Figure 5 illustrates a method for polling the
Toggle Bit.
Last Write
Yes
Load Accum
From Addr N
Compare
Accum with
Addr N
Compare
Ok?
Yes
No
Ready
5
FN8109.0
June 1, 2005
