X28HC64
64K
X28HC64
5 Volt, Byte Alterable E
2
PROM
•
•
8K x 8 Bit
FEATURES
•
•
•
•
•
•
55ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V
PP
Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS
—40 mA Active Current Max.
—200
µ
A Standby Current Max.
Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 2ms Typical
—Complete Memory Rewrite: 0.25 sec. Typical
—Effective Byte Write Cycle Time: 32
µ
s Typical
Software Data Protection
End of Write Detection
—DATA Polling
—Toggle Bit
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
JEDEC Approved Byte-Wide Pinout
DESCRIPTION
The X28HC64 is an 8K x 8 E
2
PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28HC64 is a 5V only device. The
X28HC64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle and en-
abling the entire memory to be typically written in 0.25
seconds. The X28HC64 also features
DATA
Polling and
Toggle Bit Polling, two methods providing early end of
write detection. In addition, the X28HC64 includes a
user-optional software data protection mode that further
enhances Xicor’s hardware write protect capability.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
TSOP
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A3
A4
A5
A6
A7
A12
NC
NC
VCC
NC
WE
NC
A8
A9
A11
OE
PIN CONFIGURATIONS
VCC
A12
WE
NC
NC
NC
A7
PLASTIC DIP
FLAT PACK
CERDIP
SOIC
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28HC64
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
LCC
PLCC
X28HC64
4
3
2
1 32 31 30
29
28
27
26
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
X28HC64
25
24
23
22
PGA
I/O1
I/O2
I/O3
I/O5
I/O6
12
13
15
17
18
I/O0
A0
11
10
A1
A3
A5
A2
8
A4
6
A12
2
A7
3
X28HC64
VSS
I/O4
I/O7
14
16
19
CE
20
OE
22
A10
21
A11
23
A8
25
NC
26
3857 ILL F22
10
11
12
21
13
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
9
7
3857 FHD F03
5
3857 FHD F02.1
VCC
A9
28
24
NC
1
WE
27
4
A6
3857 FHD F04
BOTTOM VIEW
© Xicor, Inc. 1994, 1995, 1996 Patents Pending
3857-3.0 8/5/97 T1/C0/D0 EW
1
Characteristics subject to change without notice
X28HC64
PIN DESCRIPTIONS
Addresses (A
0
–A
12
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X28HC64 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC64.
FUNCTIONAL DIAGRAM
65,536-BIT
E2PROM
ARRAY
PIN NAMES
Symbol
A
0
–A
12
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3857 PGM T01
X BUFFERS
LATCHES AND
DECODER
A0–A12
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
DECODER
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
WE
VCC
VSS
3857 FHD F01
CONTROL
LOGIC AND
TIMING
2
X28HC64
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The X28HC64 supports both a
CE
and
WE
controlled write cycle. That is, the address
is latched by the falling edge of either
CE
or
WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either
CE
or
WE,
which-
ever occurs first. A byte write operation, once initiated,
will automatically continue to completion, typically within
2ms.
Page Write Operation
The page write feature of the X28HC64 allows the entire
memory to be written in 0.25 seconds. Page write allows
two to sixty-four bytes of data to be consecutively written
to the X28HC64 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
page address (A
6
through A
12
) for each subsequent
valid write cycle to the part during this operation must be
the same as the initial page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
same manner as the first byte was written. Each succes-
sive byte load cycle, started by the
WE
HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding
WE.
If a subsequent
WE
HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continues to access the device within the byte load cycle
time of 100µs.
Write Operation Status Bits
The X28HC64 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
3857 FHD F11
DATA
Polling (I/O
7
)
The X28HC64 features
DATA
Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed.
DATA
Polling allows a simple
bit test operation to determine the status of the X28HC64,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
complement of that data on I/O
7
(i.e. write data = 0xxx
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28HC64 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O
6
will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
3
X28HC64
DATA
POLLING I/O
7
Figure 2.
DATA
Polling Bus Sequence
LAST
WRITE
WE
CE
OE
VIH
I/O7
HIGH Z
VOL
An
An
An
An
An
An
An
3857 FHD F12
VOH
X28HC64
READY
A0–A12
Figure 3.
DATA
Polling Software Flow
DATA
Polling can effectively reduce the time for writing
to the X28HC64. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
WRITE DATA
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
NO
READ LAST
ADDRESS
IO7
COMPARE?
YES
NO
READY
3857 FHD F13
4
X28HC64
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
I/O6
VOH
*
VOL
HIGH Z
*
X28HC64
READY
* Beginning and ending state of I/O6 will vary.
3857 FHD F14
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement
DATA
Polling.
This can be especially helpful in an array comprised of
multiple X28HC64 memories that is frequently updated.
Toggle Bit Polling can also provide a method for status
checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on
the bus. The software flow diagram in Figure 5 illustrates
a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
NO
READY
3857 FHD F15
5
