®
X28HC64
64k, 8k x 8-Bit
Data Sheet
August 28, 2009
FN8109.2
5 Volt, Byte Alterable EEPROM
The X28HC64 is an 8K x 8 EEPROM, fabricated with Intersil’s
proprietary, high performance, floating gate CMOS
technology. Like all Intersil programmable nonvolatile
memories, the X28HC64 is a 5V only device. It features the
JEDEC approved pinout for byte-wide memories, compatible
with industry standard RAMs.
The X28HC64 supports a 64-byte page write operation,
effectively providing a 32µs/byte write cycle, and enabling the
entire memory to be typically written in 0.25 seconds. The
X28HC64 also features DATA Polling and Toggle Bit Polling,
two methods providing early end of write detection. In addition,
the X28HC64 includes a user-optional software data protection
mode that further enhances Intersil’s hardware write protect
capability.
Intersil EEPROMs are designed and tested for applications
requiring extended endurance. Inherent data retention is
greater than 100 years.
Features
• 70ns access time
• Simple byte and page write
- Single 5V supply
- No external high voltages or V
PP
control circuits
- Self-timed
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- 40mA active current max.
• 200µA standby current max.
• Fast write cycle times
- 64-byte page write operation
- Byte or page write cycle: 2ms typical
- Complete memory rewrite: 0.25 sec. typical
- Effective byte write cycle time: 32µs typical
• Software data protection
• End of write detection
- DATA polling
- Toggle bit
• High reliability
- Endurance: 100000 cycles
- Data retention: 100 years
• JEDEC approved byte-wide pin out
• Pb-free available (RoHS compliant)
Pinouts
X28HC64
(28 LD PDIP, SOIC)
TOP VIEW
NC
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
8
9
10
11
12
13
14
28
27
26
25
24
23
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
5
6
7
8
9
10
11
12
A
7
X28HC64
(32 LD PLCC)
TOP VIEW
A
12
V
CC
WE
NC
NC
NC
4
3
2
1 32 31 30
29
28
27
26
25
24
23
22
A
8
A
9
A
11
NC
OE
A
10
CE
I/O
7
I/O
6
7 X28HC64 22
X28HC64
(Top View)
13
21
14 15 16 17 18 19 20
I/O
1
I/O
2
I/O
3
I/O
4
V
SS
I/O
5
NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X28HC64
Ordering Information
PART NUMBER
X28HC64J-70*
X28HC64JIZ-70* (Note 1)
X28HC64JZ-70* (Note 1)
X28HC64SIZ-70
X28HC64SZ-70 (Note 1)
X28HC64J-90*
X28HC64JI-90**
X28HC64JIZ-90* (Note 1)
X28HC64P-90
X28HC64PI-90
PART MARKING
X28HC64J-70 RR
X28HC64JI-70 ZRR
X28HC64J-70 ZRR
X28HC64SI-70 RR
X28HC64S-70 RRZ
X28HC64J-90 RR
X28HC64JI-90 RR
X28HC64JI-90 ZRR
X28HC64P-90 RR
X28HC64PI-90 RR
TEMPERATURE
RANGE (°C)
0 to +70
-40 to +85
0 to +70
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
120
90
ACCESS TIME
(ns)
70
PACKAGE
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC (Pb-free)
28 Ld SOIC (300 mil)
28 Ld SOIC (300 mil) (Pb-free)
32 Ld PLCC
32 Ld PLCC
32 Ld PLCC (Pb-free)
28 Ld PDIP
28 Ld PDIP
28 Ld PDIP (Pb-free)
28 Ld PDIP (Pb-free)
32 Ld PLCC
32 Ld PLCC
32 Ld PLCC (Pb-free)
32 Ld PLCC (Pb-free)
28 Ld PDIP
28 Ld PDIP
28 Ld PDIP (Pb-free)
28 Ld PDIP (Pb-free)
28 Ld SOIC (300 mil)
28 Ld SOIC (300 mil)
28 Ld SOIC (300 mil) (Pb-free)
28 Ld SOIC (300 mil) (Pb-free)
PKG.
DWG. #
N32.45x55
N32.45x55
N32.45x55
M28.3
M28.3
N32.45x55
N32.45x55
N32.45x55
E28.6
E28.6
E28.6
E28.6
N32.45x55
N32.45x55
N32.45x55
N32.45x55
E28.6
E28.6
E28.6
E28.6
M28.3
M28.3
M28.3
M28.3
X28HC64PIZ-90 (Notes 1, 2) X28HC64PI-90 RRZ
X28HC64PZ-90 (Notes 1, 2) X28HC64P-90 RRZ
X28HC64J-12*
X28HC64JI-12*
X28HC64JIZ-12* (Note 1)
X28HC64JZ-12* (Note 1)
X28HC64P-12
X28HC64PI-12
X28HC64J-12 RR
X28HC64JI-12 RR
X28HC64JI-12 Z RR
X28HC64J-12 RRZ
X28HC64P-12 RR
X28HC64PI-12 RR
X28HC64PIZ-12 (Notes 1, 2) X28HC64PI-12 RRZ
X28HC64PZ-12 (Notes 1, 2) X28HC64P-12 RRZ
X28HC64S-12*
,
**
X28HC64SI-12*
X28HC64SIZ-12* (Note 1)
X28HC64SZ-12 (Note 1)
X28HC64S-12 RR
X28HC64SI-12 RR
X28HC64SI-12 RRZ
X28HC64S-12 RRZ
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
***Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.
2
FN8109.2
August 28, 2009
X28HC64
Pin Descriptions
Addresses (A
0
-A
12
)
The Address inputs select an 8-bit memory location during a
read or write operation.
Device Operation
Read
Read operations are initiated by both OE and CE LOW. The
read operation is terminated by either CE or OE returning
HIGH. This two line control architecture eliminates bus
contention in a system environment. The data bus will be in
a high impedance state when either OE or CE is HIGH.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/write
operations. When CE is HIGH, power consumption is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers and
is used to initiate read operations.
Write
Write operations are initiated when both CE and WE are
LOW and OE is HIGH. The X28HC64 supports both a CE
and WE controlled write cycle. That is, the address is latched
by the falling edge of either CE or WE, whichever occurs
last. Similarly, the data is latched internally by the rising edge
of either CE or WE, whichever occurs first. A byte write
operation, once initiated, will automatically continue to
completion, typically within 2ms.
Data In/Data Out (I/O
0
-I/O
7
)
Data is written to or read from the X28HC64 through the I/O
pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC64.
TABLE 1. PIN NAMES
SYMBOL
A
0
-A
12
I/O
0
-I/O
7
WE
CE
OE
V
CC
V
SS
NC
DESCRIPTION
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
Page Write Operation
The page write feature of the X28HC64 allows the entire
memory to be written in 0.25 seconds. Page write allows two
to sixty-four bytes of data to be consecutively written to the
X28HC64 prior to the commencement of the internal
programming cycle. The host can fetch data from another
device within the system during a page write operation
(change the source address), but the page address (A
6
through A
12
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial page
address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host can
write an additional one to sixty-three bytes in the same
manner. Each successive byte load cycle, started by the WE
HIGH to LOW transition, must begin within 100µs of the
falling edge of the preceding WE. If a subsequent WE HIGH
to LOW transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is no
page write window limitation. Effectively the page write
window is infinitely wide, so long as the host continues to
access the device within the byte load cycle time of 100µs.
Block Diagram
65,536-BIT
X BUFFERS
LATCHES AND
DECODER
A
0
–A
12
ADDRESS
INPUTS
Y BUFFERS
LATCHES
AND
DECODER
I/O BUFFERS
AND LATCHES
EEPROM
ARRAY
Write Operation Status Bits
The X28HC64 provides the user two write operation status
bits. These can be used to optimize a system write cycle
time. The status bits are mapped onto the I/O bus as shown
in Figure 1.
I/O
DP
TB
5
4
3
2
1
0
CE
OE
WE
V
CC
V
SS
CONTROL
LOGIC AND
TIMING
I/O
0
–I/O
7
DATA INPUTS/OUTPUTS
RESERVED
TOGGLE BIT
DATA POLLING
FIGURE 1. STATUS BIT ASSIGNMENT
3
FN8109.2
August 28, 2009
X28HC64
DATA Polling (I/O
7
)
The X28HC64 features DATA Polling as a method to indicate
to the host system that the byte write or page write cycle has
completed. DATA Polling allows a simple bit test operation to
determine the status of the X28HC64, eliminating additional
interrupt inputs or external hardware. During the internal
programming cycle, any attempt to read the last byte written
will produce the complement of that data on I/O
7
(i.e. write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true data.
Toggle Bit (I/O
6
)
The X28HC64 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O
6
will toggle from HIGH to LOW and
LOW to HIGH on subsequent attempts to read the device.
When the internal cycle is complete the toggling will cease
and the device will be accessible for additional read or write
operations.
DATA Polling I/O
7
WE
Last
Write
CE
OE
V
IH
I/O
7
HIGH Z
V
OL
A
0
–A
12
V
OH
X28HC64
Ready
An
An
An
An
An
An
An
FIGURE 2. DATA POLLING BUS SEQUENCE
WRITE DATA
DATA Polling can effectively reduce the time for writing to the
X28HC64. The timing diagram in Figure 2 illustrates the
sequence of events on the bus. The software flow diagram in
Figure 3 illustrates one method of implementing the routine.
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
COMPARE?
YES
NO
READY
FIGURE 3. DATA POLLING SOFTWARE FLOW
4
FN8109.2
August 28, 2009
X28HC64
The Toggle Bit I/O
6
WE
LAST
WRITE
CE
OE
I/O
6
V
OH
*
V
OL
HIGH Z
*
X28HC64
READY
* BEGINNING AND ENDING STATE OF I/O
6
WILL VARY.
FIGURE 4. TOGGLE BIT BUS SEQUENCE
Hardware Data Protection
LAST WRITE
The X28HC64 provides two hardware features that protect
nonvolatile data from inadvertent writes.
• Default V
CC
Sense—All write functions are inhibited when
V
CC
is 3V typically.
• Write Inhibit—Holding either OE LOW, WE HIGH, or CE
HIGH will prevent an inadvertent write cycle during power-
up and power-down, maintaining data integrity.
YES
LOAD ACCUM
FROM ADDR N
Software Data Protection
COMPARE
ACCUM WITH
ADDR N
COMPARE
OK?
YES
NO
The X28HC64 offers a software controlled data protection
feature. The X28HC64 is shipped from Intersil with the software
data protection NOT ENABLED; that is, the device will be in the
standard operating mode. In this mode data should be
protected during power-up/-down operations through the use of
external circuits. The host would then have open read and write
access of the device once V
CC
was stable.
The X28HC64 can be automatically protected during power-
up and power-down without the need for external circuits by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation utilizing the software algorithm. This circuit is
nonvolatile and will remain set for the life of the device,
unless the reset command is issued.
Once the software protection is enabled, the X28HC64 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
READY
FIGURE 5. TOGGLE BIT SOFTWARE FLOW
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC64 memories that is frequently
updated. Toggle Bit Polling can also provide a method for
status checking in multiprocessor applications. The timing
diagram in Figure 4 illustrates the sequence of events on the
bus. The software flow diagram in Figure 5 illustrates a
method for polling the Toggle Bit.
Software Algorithm
Selecting the software data protection mode requires the
host system to precede data write operations by a series of
three write operations to three specific addresses. Refer to
Figure 6 and 7 for the sequence. The three-byte sequence
opens the page write window, enabling the host to write from
one to sixty-four bytes of data. Once the page load cycle has
been completed, the device will automatically be returned to
the data protected state.
FN8109.2
August 28, 2009
5
RF/无线
