New Features
• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor
X40010/X40011/X40014/X40015
Dual Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V
CC
= 1V
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
• Selectable power on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval (25ms, 200ms,
1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC, TSSOP
APPLICATIONS
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Computers
—Network Servers
DESCRIPTION
The X40010/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to V
CC
activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low V
CC
detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
V
CC
falls below the minimum V
TRIP1
point. RESET/
RESET is active until V
CC
returns to proper operating
level and stabilizes. A second voltage monitor circuit
tracks the unregulated supply to provide a power fail
warning or monitors different power supply voltage.
Three common low voltage combinations are avail-
able, however, Xicor’s unique circuits allows the
BLOCK DIAGRAM
Watchdog Timer
and
Reset Logic
SDA
Data
Register
Command
Decode Test
& Control
Logic
Threshold
Reset Logic
Fault Detection
Register
Status
Register
WDO
SCL
V
CC
(V1MON)
+
User Programmable
V
TRIP1
User Programmable
V
TRIP2
-
+
-
V2MON
V
CC
Power on,
Low Voltage
Reset
Generation
RESET
X40010/14
RESET
X40011/15
V2MON
V2FAIL
*X40010/11 = V2MON*
X40014/15 = V
CC
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X40010/X40011/X40014/X40015
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The device features a 2-wire interface and software
protocol allowing operation on an I
2
C
®
bus.
Dual Voltage Monitors
Device
X40010/11
-A
-B
-C
X40014/15
-A
-B
-C
Expected System Voltages
5V; 3V or 3.3V
5V; 3V
3V; 3.3V; 1.8V
3V; 3.3V; 1.5V
3V; 1.5V
3V or 3.3V; 1.1 or 1.2V
Vtrip1(V)
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.85–2.95*
2.0–4.75*
2.85–2.95*
2.55–2.65*
2.85–2.95*
Vtrip2(V)
1.70–4.75
2.85–2.95
2.55–2.65
1.65–1.75
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
POR (system)
RESET = X40010
RESET = X40011
RESET = X40014
RESET = X40015
*Voltage monitor requires V
CC
to operation. Others are independent of V
CC
.
PIN CONFIGURATION
X40010/14, X40011/15
8-Pin SOIC
V2FAIL
V2MON
RESET/RESET
V
SS
1
2
3
4
8
7
6
5
V
CC
WDO
SCL
SDA
WDO
V
CC
V2FAIL
V2MON
X40010/14, X40011/15
8-Pin TSSOP
1
2
3
4
8
7
6
5
SCL
SDA
V
SS
RESET/RESET
PIN DESCRIPTION
Pin
SOIC TSSOP Name
1
2
3
4
Function
3
5
4
6
V2FAIL
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power up reset delay circuitry on this pin.
V2MON
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or
V
CC
when not used.The V2MON comparator is supplied by V2MON (X40010/11) or by V
CC
Input
(X40014/15).
RESET/
RESET Output.
(X40011/15) This is an active LOW, open drain output which goes active when-
RESET ever V
CC
falls below V
TRIP1
. It will remain active until V
CC
rises above V
TRIP1
and for the t
PURST
thereafter.
RESET Output.
(X40010/14) This is an active HIGH CMOS output which goes active whenever
V
CC
falls below V
TRIP1
. It will remain active until
V
CC
rises above V
TRIP1
and for the t
PURST
there-
after.
V
SS
Ground
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X40010/X40011/X40014/X40015
PIN DESCRIPTION
(Continued)
Pin
SOIC TSSOP Name
5
7
SDA
Function
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to
LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this tran-
sition within the watchdog time out period results in WDO going active.
Serial Clock.
The Serial Clock controls the serial bus timing for data input and output.
WDO Output.
WDO is an active LOW, open drain output which goes active whenever the
watchdog timer goes active.
Supply Voltage
6
7
8
8
1
2
SCL
WDO
V
CC
PRINCIPLES OF OPERATION
Power On Reset
Application of power to the X40010/11/14/15 activates a
Power On Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabili-
zation of the oscillator.
– It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When V
CC
exceeds the device V
TRIP1
threshold value for
t
PURST
(selectable) the circuit releases the RESET
(X40011) and RESET (X40010) pin allowing the system
to begin operation.
Low Voltage V
CC
(V1 Monitoring)
During operation, the X40010/11/14/15 monitors the V
CC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V
TRIP1
. The RESET/RESET
signal prevents the microprocessor from operating in a
power fail or brownout condition. The V1FAIL signal
remains active until the voltage drops below 1V. It also
remains active until V
CC
returns and exceeds V
TRIP1
for
t
PURST
.
Low Voltage V2 Monitoring
The X40010/11/14/15 also monitors a second voltage
level and asserts V2FAIL if the voltage falls below a
preset minimum V
TRIP2
. The V2FAIL signal is either
ORed with RESET to prevent the microprocessor from
operating in a power fail or brownout condition or used to
interrupt the microprocessor with notification of an
REV 1.3.5 2/11/04
impending power failure. For the X40010/11 the V2FAIL
signal remains active until the V
CC
drops below 1V (V
CC
falling). It also remains active until V2MON returns and
exceeds V
TRIP2
by 0.2V. This voltage sense circuitry
monitors the power supply connected to the V2MON pin.
If V
CC
= 0, V2MON can still be monitored.
For the X40014/15 devices, the V2FAIL signal remains
actice until V
CC
drops below 1Vx and remains active until
V2MON returns and exceeds V
TRIP2
. This sense circuitry
is powered by V
CC
. If V
CC
= 0, V2MON cannot be moni-
tored.
Figure 1. Two Uses of Multiple Voltage Monitoring
X40011-A
5V
Reg
V
CC
RESET
V2MON
(2.9V)
V2FAIL
V
CC
V2MON
6–10V
1M
1M
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
V
CC
X40014-C
Unreg.
Supply
3.3V
Reg
1.2V
Reg
V
CC
RESET
V2MON
V2FAIL
System
Reset
Notice:
No external components required to monitor two voltages.
Characteristics subject to change without notice.
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X40010/X40011/X40014/X40015
Figure 2. V
TRIPX
Set/Reset Conditions
V
TRIPX
(X = 1, 2)
V
CC
/V2MON
V
P
WDO
SCL
0
7
0
7
0
7
SDA
A0h
00h
t
WC
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a WDO signal going active. The state of two non-
volatile control bits in the Status Register determines
the watchdog timer period. The microprocessor can
change these watchdog bits by writing to the X40010/
11/14/15 control register (also refer to page 19).
Figure 3. Watchdog Restart
.6µs
SCL
1.3µs
points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
Setting a V
TRIPx
Voltage (x=1, 2)
There are two procedures used to set the threshold
voltages (V
TRIPx
), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present V
TRIPx
is 2.9 V and the new
V
TRIPx
is 3.2 V, the new voltage can be stored directly
into the V
TRIPx
cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the V
TRIPx
voltage before setting the new value.
Setting a Higher V
TRIPx
Voltage (x=1, 2)
To set a V
TRIPx
threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired V
TRIPx
threshold voltage to the corre-
sponding input pin Vcc(V1MON), or V2MON. The
Vcc(V1MON) and V2MON must be tied together during
this sequence. Then, a programming voltage (Vp) must
be applied to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h, followed by the Byte Address 01h for
V
TRIP1
and 09h for V
TRIP2
, and a 00h Data Byte in
order to program V
TRIPx
. The STOP bit following a
valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
Note:
This operation does not corrupt the memory
array.
SDA
Timer Start
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40010/11/14/15is shipped with standard V1 and
V2 threshold (V
TRIP1,
V
TRIP2
) voltages. These values
will not change over normal operating and storage con-
ditions. However, in applications where the standard
thresholds are not exactly right, or if higher precision is
needed in the threshold value, the X40010/11/14/15trip
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Characteristics subject to change without notice.
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X40010/X40011/X40014/X40015
Setting a Lower V
TRIPx
Voltage (x=1, 2)
In order to set V
TRIPx
to a lower voltage than the
present value, then V
TRIPx
must first be “reset” accord-
ing to the procedure described below. Once V
TRIPx
has been “reset”, then V
TRIPx
can be set to the desired
voltage using the procedure described in “Setting a
Higher V
TRIPx
Voltage”.
Resetting the V
TRIPx
Voltage
To reset a V
TRIPx
voltage, apply the programming volt-
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
TRIP1
and 0Bh for V
TRIP2
, followed by 00h for the
Data Byte in order to reset V
TRIPx
. The STOP bit fol-
lowing a valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to
complete the operation.
After being reset, the value of V
TRIPx
becomes a nomi-
nal value of 1.7V or lesser.
Note:
This operation does not corrupt the memory
array.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
Figure 4. Sample V
TRIP
Reset Circuit
V
P
Adjust
V2FAIL
RESET
V
TRIP1
Adj.
V
TRIP2
Adj.
4.7K
1
8
Run
SCL
SDA
3
SOIC
7
2
X4001x
6
4
5
µC
The Control Register is accessed with a special pre-
amble in the slave byte (1011) and is located at
address 1FFh. It can only be modified by performing a
byte write operation directly to the address of the regis-
ter and only one data byte is allowed for each register
write operation. Prior to writing to the Control Register,
the WEL and RWEL bits must be set using a two step
process, with the whole sequence requiring 3 steps.
See "Writing to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The X40010/
11/14/15 will not acknowledge any data bytes written
after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should sup-
ply a stop condition to be consistent with the bus proto-
col, but a stop is not required to end this operation.
7
6
5
WD0
4
BP
3
0
2
1
0
PUP1 WD1
RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
REV 1.3.5 2/11/04
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Characteristics subject to change without notice.
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