X4003, X4005
CPU Supervisor
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FN8113
Rev 2.00
June 30, 2008
These devices combine three popular functions; Power-on
Reset Control, Watchdog Timer and Supply Voltage
Supervision. This combination lowers system cost, reduces
board space requirements and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
CC
trip point.
RESET/RESET is asserted until V
CC
returns to proper
operating level and stabilizes. Five industry standard V
TRIP
thresholds are available; however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements, or to fine-tune the threshold for applications
requiring higher precision.
Features
• Selectable watchdog timer
- Select 200ms, 600ms, 1.4s, off
• Low V
CC
detection and reset assertion
- Five standard reset threshold voltages nominal 4.62V,
4.38V, 2.92V, 2.68V, 1.75V
- Adjust low V
CC
reset threshold voltage using special
programming sequence
- Reset signal valid to V
CC
= 1V
• Low power CMOS
- 12µA typical standby current, watchdog on
- 800nA typical standby current watchdog off
- 3mA active current
• 400kHz I
2
C interface
• 1.8V to 5.5V power supply operation
• Available packages
- 8 Ld SOIC
- 8 Ld MSOP
• Pb-free available (RoHS compliant)
Pinout
X4003, X4005
(8 LD SOIC, MSOP)
TOP VIEW
NC
NC
RESET/RESET*
V
SS
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
*RESET APPLIES TO X4003
RESET APPLIES TO X4005
Block Diagram
WATCHDOG TRANSITION
DETECTOR
WP
DATA
REGISTER
COMMAND
DECODE AND
CONTROL
LOGIC
V
CC
THRESHOLD
RESET LOGIC
V
CC
V
TRIP
WATCHDOG
TIMER RESET
RESET (X4003)
CONTROL
REGISTER
RESET AND
WATCHDOG
TIMEBASE
RESET (X4005)
SDA
SCL
+
-
POWER-ON AND
LOW VOLTAGE
RESET
GENERATION
FN8113 Rev 2.00
June 30, 2008
Page 1 of 16
X4003, X4005
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X4003M8-4.5A
X4003M8Z-4.5A
(Note)
X4003S8-4.5A
X4003S8Z-4.5A
(Note)
X4003M8I-4.5A
X4003M8IZ-4.5A
(Note)
X4003S8I-4.5A
X4003S8IZ-4.5A
(Note)
X4003M8
PART
MARKING
ACH
DAH
X4003 AL
PART NUMBER
RESET
(ACTIVE HIGH)
X4005M8-4.5A
X4005M8Z-4.5A
(Note)
X4005S8-4.5A
PART
V
CC
RANGE V
TRIP
RANGE TEMP. RANGE
MARKING
(V)
(V)
(°C)
ACQ
DAP
X4005 AL
X4005 ZAL
ACR
4.5 to 5.5
4.5 to 4.75
0 to +70
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
4.25 to 4.5
0 to +70
0 to +70
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
2.7 to 5.5
2.85 to 3.0
0 to +70
0 to +70
0 to +70
0 to +70
2.55 to 2.7
0 to +70
0 to +70
0 to +70
0 to +70
PACKAGE
8 Ld MSOP
(3.0mm)
PKG. DWG. #
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4003 ZAL X4005S8Z-4.5A
(Note)
ACI
DAD
X4003 AM
X4005M8I-4.5A
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
X4005M8IZ-4.5A DAM
(Note)
X4005S8I-4.5A
X4005 AM
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4003 ZAM X4005S8IZ-4.5A X4005 ZAM
(Note)
ACJ
X4005M8
ACS
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
X4003M8Z (Note) DAE
X4003S8
X4003
X4005M8Z (Note) DER
X4005S8
X4005
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4003S8Z (Note) X4003 Z
X4003M8I
ACK
X4005S8Z (Note) X4005 Z
X4005M8I
X4005M8IZ
(Note)
X4005S8I
X4005S8IZ
(Note)
X4005M8-2.7A
X4005M8Z-2.7A
(Note)
X4005S8-2.7A
ACT
DAJ
X4005 I
X4005 ZI
ACU
DAO
X4005 AN
X4005 ZAN
ACW
DAN
X4005 F
X4005 ZF
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
X4003M8IZ (Note) DAA
X4003S8I
X4003 I
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4003S8IZ (Note) X4003 ZI
X4003M8-2.7A
X4003M8Z-2.7A
(Note)
X4003S8-2.7A
X4003S8Z-2.7A
(Note)
X4003M8-2.7
X4003M8Z-2.7
(Note)
X4003S8-2.7
X4003S8Z-2.7
(Note)
ACL
DAG
X4003 AN
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
X4003 ZAN X4005S8Z-2.7A
(Note)
ACN
DAF
X4003 F
X4003 ZF
X4005M8-2.7
X4005M8Z-2.7
(Note)
X4005S8-2.7
X4005S8Z-2.7
(Note)
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
FN8113 Rev 2.00
June 30, 2008
Page 2 of 16
X4003, X4005
Ordering Information
(Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X4003S8I-2.7A
X4003S8IZ-2.7A
(Note)
X4003M8I-2.7A
X4003M8IZ-2.7A
(Note)
X4003S8I-2.7
X4003S8IZ-2.7
(Note)
X4003M8I-2.7
X4003M8IZ-2.7
(Note)
PART
MARKING
X4003 AP
PART NUMBER
RESET
(ACTIVE HIGH)
X4005S8I-2.7A
PART
V
CC
RANGE V
TRIP
RANGE TEMP. RANGE
MARKING
(V)
(V)
(°C)
X4005 AP
2.7 to 3.6
2.85 to 3.0
-40 to +85
-40 to +85
-40 to +85
-40 to +85
2.55 to 2.7
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PACKAGE
8 Ld SOIC
(150 mil)
PKG. DWG. #
MDP0027
X4003 ZAP X4005S8IZ-2.7A X4005 ZAP
(Note)
ACM
DAC
X4003 G
X4003 ZG
ACO
DAB
X4005M8I-2.7A
ACV
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
X4005M8IZ-2.7A DAL
(Note)
X4005S8I-2.7
X4005S8IZ-2.7
(Note)
X4005M8I-2.7
X4005M8IZ-2.7
(Note)
X4005 G
X4005 ZG
ACX
DAK
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
8 Ld SOIC
(150 mil)
MDP0027
8 Ld SOIC
MDP0027
(150 mil) (Pb-free)
8 Ld MSOP
(3.0mm)
M8.118
8 Ld MSOP
M8.118
(3.0mm) (Pb-free)
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
Pin Descriptions
PIN
NUMBER
(MSOP)
1
2
3
NAME
NC
NC
RESET/RESET
No internal connections
No internal connections
Reset Output.
RESET/RESET is an active LOW/HIGH, open drain output which goes active whenever V
CC
falls below
the minimum V
CC
sense level. It will remain active until V
CC
rises above the minimum V
CC
sense level for 250ms.
RESET/RESET goes active if the watchdog timer is enabled and SDA remains either HIGH or LOW longer than the
selectable Watchdog time out period. A falling edge of SDA, while SCL also toggles from HIGH to LOW followed by a
stop condition resets the watchdog timer. RESET/RESET goes active on power-up and remains active for 250ms after
the power supply stabilizes.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It has an open drain output and
may be wire ORed with other open drain or open collector outputs. This pin requires a pull-up resistor and the input buffer
is always active (not gated).
Watchdog Input.
A HIGH to LOW transition on the SDA while SCL also toggles from HIGH to LOW follow by a stop
condition resets the watchdog timer. The absence of this procedure within the watchdog time-out period results in
RESET/RESET going active.
Serial Clock.
The serial clock controls the serial bus timing for data input and output.
Write Protect.
WP HIGH prevents changes to the watchdog timer setting.
Supply voltage
FUNCTION
4
5
V
SS
SDA
6
7
8
SCL
WP
V
CC
FN8113 Rev 2.00
June 30, 2008
Page 3 of 16
X4003, X4005
Principles of Operation
Power-on Reset
Application of power to the X4003/X4005 activates a power-on
reset circuit that pulls the RESET/RESET pin active. This signal
provides several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to stabilization
of the oscillator.
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
When V
CC
exceeds the device V
TRIP
threshold value for 200ms
(nominal) the circuit releases RESET/RESET, allowing the
system to begin operation.
SCL
0.6µs
0.6µs
SDA
START
CONDITION
RESTART
STOP
CONDITION
FIGURE 1. WATCHDOG RESTART
V
CC
Threshold Reset Procedure
The X4003/X4005 is shipped with a standard V
CC
threshold
(V
TRIP
) voltage. This value will not change over normal
operating and storage conditions. However, in applications
where the standard V
TRIP
is not exactly right, or if higher
precision is needed in the V
TRIP
value, the X4003/X4005
threshold may be adjusted. The procedure is described in the
following and uses the application of a nonvolatile control
signal.
Low Voltage Monitoring
During operation, the X4003/X4005 monitors the V
CC
level and
asserts RESET/RESET if supply voltage falls below a preset
minimum V
TRIP
. The RESET/RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition. The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until V
CC
returns
and exceeds V
TRIP
for 200ms.
Setting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a higher voltage
value. For example, if the current V
TRIP
is 4.4V and the new
V
TRIP
is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it is
necessary to reset the trip point before setting the new value.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold
voltage to the V
CC
pin and tie the WP pin to the programming
voltage V
P
. Then write data 00hto address 01h. The stop bit
following a valid write operation initiates the V
TRIP
programing
sequence. Bring WP LOW to complete the operation.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the SDA and SCL pins. The microprocessor
must toggle the SDA pin HIGH to LOW periodically, while SCL
also toggles from HIGH to LOW (this is a start bit) followed by a
stop condition prior to the expiration of the watchdog time-out
period to prevent a RESET/RESET signal. The state of two
nonvolatile control bits in the control register determine the
watchdog timer period. The microprocessor can change these
watchdog bits, or they may be “locked” by tying the WP pin
HIGH.
WP
V
P
= 15V TO 18V
0
SCL
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SDA
A0h
01h
00h
FIGURE 2. SET V
TRIP
LEVEL SEQUENCE (V
CC
= DESIRED V
TRIP
VALUE)
FN8113 Rev 2.00
June 30, 2008
Page 4 of 16
X4003, X4005
WP
V
P
= 15V TO 18V
0
SCL
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
SDA
A0h
03h
00h
FIGURE 3. RESET V
TRIP
LEVEL SEQUENCE (V
CC
> 3V. WP = 15V TO 18V)
V
P
4.7k
RESET/RESET
V
TRIP
ADJ.
1
2
3
4
X4003
X4005
8
7
6
5
RUN
SCL
SDA
ADJUST
µC
FIGURE 4. SAMPLE V
TRIP
RESET CIRCUIT
Resetting the V
TRIP
Voltage
This procedure is used to set the V
TRIP
to a “native” voltage
level. For example, if the current V
TRIP
is 4.4V and the new
V
TRIP
must be 4.0V, then the V
TRIP
must be reset. When V
TRIP
is reset, the new V
TRIP
is something less than 1.7V. This
procedure must be used to set the voltage to a lower value.
To reset the new V
TRIP
voltage, apply the desired V
TRIP
threshold voltage to the V
CC
pin and tie the WP pin to the
programming voltage V
P
. Then write 00h to address 03h. The
stop bit of a valid write operation initiates the V
TRIP
programming sequence. Bring WP LOW to complete the
operation.
FN8113 Rev 2.00
June 30, 2008
Page 5 of 16
