DATASHEET
X45620
Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FEATURES
• Dual voltage monitoring
• Active low reset outputs
• Two standard reset threshold voltages
—Factory programmable threshold
• Lowline Output — zero delayed POR
• Reset signal valid to V
CC
= 1V
• System battery switch-over circuitry
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• 256Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
programmable Block Lock
™
protection
—In circuit programmable ROM mode
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 400kHz 2-wire Interface
• 2.7V to 5.5V power supply operation
• Available package — 20-lead TSSOP
BLOCK DIAGRAM
V
OUT
V2 Monitor
Logic
V
TRIP2
-
+
FN8250
Rev 0.00
July 29, 2005
• Dual supervisor
• Battery switch and output
DESCRIPTION
The Intersil X45620 combines power-on reset control,
battery switch circuit, watchdog timer, supply voltage
supervision, secondary voltage supervision, block lock
protect and serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to
stabilize before the processor can execute code.
A system battery switch circuit compares V
CC
(V1MON)
with V
BATT
input and connects V
OUT
to whichever is
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X45620
can drive 50mA from V
CC
and 250µA from V
BATT
. The
device switches to V
BATT
when V
CC
drops below the
low V
CC
voltage threshold and V
BATT >
V
CC
.
V2MON
V2FAIL
Watchdog Transition
Detector
WP
Data
Register
Address-Decoder
Command
Decode, Test
& Control
Logic
Protect Logic
Status
Register
EEPROM
Array
WDO
Watchdog
Timer Reset
SDA
SCL
Reset &
Watchdog
Timebase
BATT-ON
512 X 512
(32K X 8 Bit)
S0
S1
Device
Select
Logic
V
OUT
V
CC
Monitor
Logic
V
TRIP1
-
+
RESET/MR
V
CC
(V1MON)
V
OUT
V
BATT
System
Battery
Switch
Power-on,
Low Voltage
Reset
Generation
LOWLINE
FN8250 Rev 0.00
July 29, 2005
Page 1 of 20
X45620
DESCRIPTION
(Continued)
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The device’s low V
CC
detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when V
CC
(V1MON) falls below the minimum
V
CC
trip point (V
TRIP1
). RESET is asserted until V
CC
returns to proper operating level and stabilizes. A sec-
ond voltage monitor circuit tracks the unregulated supply
or monitors a second power supply voltage to provide a
power fail warning. Intersil’s unique circuits allow the
threshold for either voltage monitor to be reprogrammed
to meet special needs or to fine-tune the threshold for
applications requiring higher precision. (Contact factory
for custom V
TRIP
options)
Ordering Information
V
CC
Range
4.75–5.5V
2.7–5.5V
PIN CONFIGURATION
20-Pin TSSOP
S0
S1
NC
LOWLINE
NC
V2FAIL
V2MON
RESET/MR
WDO
V
SS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
(V1MON)
WP
NC
BATT-ON
V
OUT
V
BATT
SCL
NC
NC
SDA
V
TRIP1
Range
4.5–4.75V
2.55–2.7V
V
TRIP2
Range
2.55–2.7V
1.7–1.80V
Package
20L TSSOP
20L TSSOP
Operating
Temperature Range
0°C–70°C
-40°C–85°C
0°C–70°C
-40°C–85°C
Part Number
X45620V20
X45620V20I
X45620V20-2.7
X45620V20I-2.7
PIN DESCRIPTION
Pin
1
2
3
4
5
6
7
Name
S
0
S
1
NC
LOWLINE
NC
V2FAIL
V2MON
Function
Device Select Input.
This pin has an internal pull down resistor. (>10M typical)
Device Select Input.
This pin has an internal pull down resistor. (>10M typical)
No internal connections
Low V
CC
Detect.
This open drain output signal goes LOW when V
CC
< V
TRIP1
and immediately
goes HIGH when V
CC
> V
TRIP1
.
No internal connections
V2 Voltage Fail Output.
This open drain output goes LOW when V2MON is less than V
TRIP2
and
goes HIGH when V2MON exceeds V
TRIP2
. There is no power-up reset delay circuitry on this pin.
V2 Voltage Monitor Input.
When the V2MON input is less than the V
TRIP2
voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V
SS
or V
CC
when not used.
FN8250 Rev 0.00
July 29, 2005
Page 2 of 20
X45620
PIN DESCRIPTION
(Continued)
Pin
8
Name
RESET
/MR
Function
Reset Output/Manual Reset Input.
This is an Input/Output pin.
RESET Output.
This is an active LOW, open drain output which goes active whenever V
CC
falls
below the minimum V
CC
sense level. When RESET is active communication to the device is interrupt-
ed. RESET remains active until V
CC
rises above the minimum V
CC
sense level for t
PURST
. RESET
also goes active on power-up and remains active for t
PURST
after the power supply stabilizes.
MR Input.
This is an active LOW debounced input. When MR is active, the RESET pins are assert-
ed. When MR is released, the RESET remains asserted for t
PURST
, and then released.
Watchdog Output.
WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
Ground
Serial Data.
SDA is a bidirectional pin used to transfer data into and out of the device. It is an open
drain output, requires the use of a pull-up resistor.
Serial Clock.
The SCL input is used to clock all data into and out of the device.
No internal connections
Battery Supply Voltage.
This input provides a backup supply in the event of a failure of the pri-
mary V
CC
voltage. The V
BATT
voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect V
BATT
to ground.
Output Voltage.
V
OUT
= V
CC
if V
CC
> V
TRIP1
.
IF V
CC
< V
TRIP1
, then,
V
OUT
= V
CC
if V
CC
> V
BATT
+0.03
V
OUT
= V
BATT
if V
CC
< V
BATT
-0.03
Note:
There is hysteresis around V
BATT
± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
Battery On.
This CMOS output goes HIGH when the V
OUT
switches to V
BATT
and goes LOW
when V
OUT
switches to V
CC
. It is used to drive a external P-channel FET when V
CC
= V
OUT
and
current requirements are greater than 50mA.
The purpose of this output is to drive an external FET to get higher operating currents when the
V
CC
supply is fully functional. In the event of a V
CC
failure, the battery voltage is applied to the
V
OUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data-there is no
communication at this time.
No Connect
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits.
This pin has an internal pull down
resistor. (>10M typical)
9
10
11
14
12–13
15
WDO
V
SS
SDA
SCL
NC
V
BATT
16
V
OUT
17
BATT-ON
18
19
NC
WP
20
V
CC
(V1MON)
Supply Voltage/V1 Voltage Monitor Input.
When the V1MON input is less than the VTRIP1
voltage, RESET and LOWLINE go ACTIVE.
FN8250 Rev 0.00
July 29, 2005
Page 3 of 20
X45620
ABSOLUTE MAXIMUM RATINGS
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with
respect to V
SS
...................................... -1.0V to +6V
D.C. output current
(all output pins except V
OUT
)............................. 5mA
D.C. output current V
OUT
.................................... 50mA
Lead temperature (soldering, 10 seconds) ........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Min
0°C
-40°C
Max
70°C
+85°C
Device Option
-2.7
Blank
Supply Voltage
2.7V-5.5V
4.75V-5.5V
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified)
Limits
Symbol
I
CC1
Parameter
V
CC
Supply Current (Active)
(Excludes I
OUT
) Read Memory array
(Excludes I
OUT
) Write nonvolatile
Memory
V
CC
Supply Current (Passive)
(Excludes I
OUT
)
V
CC
Current (Battery Backup Mode)
(Excludes I
OUT
)
V
BATT
Current (Excludes I
OUT
)
V
BATT
Current (Excludes I
OUT
)
(Battery Backup Mode)
Min
Typ (6)
Max
1.5
3.0
Unit
mA
Test Conditions
SCL = 400kHz
V
OUT
, RESET,
LOWLINE = Open
Note 1
SDA = V
CC
, Any Input =
V
SS
or V
CC
: V
OUT
,
RESET, LOWLINE =
Open, Note 2
V
BATT
= 2.8V, V
OUT
, RE-
SET = Open, Note 4, 1
V
OUT
= V
CC
, Note 4
V
OUT
= V
BATT
,
V
BATT
= 2.8V
V
OUT
, RESET = Open,
Note 4
I
OUT
= -5mA
I
OUT
= -50mA
I
OUT
= -250µA
I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V)
Power-up
Power-down, Note 4
X45620
X45620-2.7
X45620
X45620-2.7
I
CC2
µA
50
1
1
50
µA
µA
µA
I
CC3
I
BATT1
I
BATT2
V
OUT1
V
OUT2
V
OLB
V
BSH
V
TRIP1
V
TRIP2
Output Voltage (V
CC
> V
BATT
+ 0.03V or
V
CC
> V
TRIP1
Output Voltage (V
CC
< V
BATT
+ 0.03V
and V
CC
< V
TRIP1
) {Battery Backup}
Output (BATT-ON) LOW Voltage
Battery Switch Hysteresis
(V
CC
< V
TRIP1
)
V
CC
Reset Trip Point Voltage
V2MON Reset Trip Point Voltage
V
CC
– 0.05
V
CC
– 0.5
V
BATT
– 0.2
V
CC
– 0.02
V
CC
– 0.2
V
V
V
0.4
30
-30
4.5
2.55
2.55
1.7
4.62
2.62
2.62
1.75
4.75
2.7
2.7
1.8
V
mV
mV
V
V
FN8250 Rev 0.00
July 29, 2005
Page 4 of 20
X45620
D.C. OPERATING CHARACTERISTICS
(CONTINUED)
(Over recommended operating conditions unless otherwise specified)
Limits
Symbol
V
OLR
Parameter
Output (RESET, LOWLINE, WDO, V2-
FAIL) LOW Voltage
Input (SDA, S0, S1, SCL, WP) LOW
Voltage
Input (SDA, S0, S1, SCL, WP) HIGH
Voltage
Input Leakage Current (SDA, S1, S0,
SCL, WP)
Output (SDA) LOW Voltage
Min
Typ (6)
Max
0.4
Unit
V
Test Conditions
I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V)
Note 3
Note 3
Two Wire Interface
V
IL
V
IH
I
LI
V
OLS
-0.5
V
CC
x 0.7
V
CC
x 0.3
V
CC
+ 0.5
±10
0.4
V
V
µA
V
I
OL
= 3.0mA (5V)
I
OL
= 1.0mA (3V), Note 4
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t
WC
after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t
WC
after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) V
IL
min. and V
IH
max. are for reference only and are not tested.
(4) This parameter is guaranteed by characterization.
CAPACITANCE
T
A
= +25°C, f = 1MHz, V
CC
= 5V
Symbol
C
OUT
C
IN
Test
Output Capacitance (SDA, RESET, V2FAIL, LOWLINE, BATT-ON, WDO)
Input Capacitance (SDA, SCL, S0, S1, WP)
Max
8
6
Unit
pF
pF
Conditions
V
OUT
= 0V,
Note 1, 4
V
IN
= 0V,
Note 1, 4
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
CC
V
CC
V
CC
1.53k
BATT-ON
30pF
30pF
4481
A.C. TEST CONDITIONS
Input pulse levels
Input rise and fall times
Input and output timing level
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
1.53k
SDA
RESET
V2FAIL
LOWLINE
WDO
FN8250 Rev 0.00
July 29, 2005
Page 5 of 20
嵌入式系统
