®
X5043, X5045
4K, 512 x 8 Bit
Data Sheet
March 16, 2006
FN8126.2
CPU Supervisor with 4K SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor executes code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
CC
trip point.
RESET/RESET is asserted until V
CC
returns to proper
operating level and stabilizes. Four industry standard V
TRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as 512 x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write
™
cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Features
• Low V
CC
Detection and Reset Assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low V
CC
reset threshold voltage using
special programming sequence.
- Reset signal valid to V
CC
= 1V
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <10µA max standby current, watchdog off
• 4Kbits of EEPROM–1M Write Cycle Endurance
• Save Critical Data with Block Lock
™
Memory
- Protect 1/4, 1/2, all or none of EEPROM array
• Built-in Inadvertent Write Protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time
- 16-byte page write mode
- 5ms write cycle time (typical)
• Available Packages
- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP
- 14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5043, X5045
Typical Application
2.7-5.0V
VCC
VCC
uC
X5043
RESET
CS
SCK
SI
SO
WP
VSS
10K
RESET
SPI
VSS
Block Diagram
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Timer
Reset
RESET (X5043)
RESET (X5045)
V
CC
V
TRIP
+
-
X5043, X5045
STANDARD V
TRIP
LEVEL
Watchdog
Transition
Detector
4.63V (+/-2.5%)
4.38V (+/-2.5%)
2.93V (+/-2.5%)
2.63V (+/-2.5%)
SUFFIX
-4.5A
-4.5
-2.7A
-2.7
CS/WDI
SI
SO
SCK
WP
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
4Kbits
See “Ordering Information” on page 3. for
more details
For Custom Settings, call Intersil.
2
FN8126.2
March 16, 2006
X5043, X5045
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5043P-4.5A
X5043PZ-4.5A (Note)
X5043PI-4.5A
X5043S8-4.5A
PART
MARKING
X5043P AL
X5043P AM
X5043 AL
PART NUMBER
RESET
(ACTIVE HIGH)
X5045P-4.5A
X5045PI-4.5A
X5045S8-4.5A
X5045S8Z-4.5A
(Note)
X5045S8I-4.5A*
X5045S8IZ-4.5A*
(Note)
X5045M8-4.5A
X5045M8Z-4.5A
(Note)
X5045M8I-4.5A
X5045M8IZ-4.5A
(Note)
X5045V14I-4.5A
PART
MARKING
X5045P AL
X5045P AM
X5045 AL
X5045 Z AL
X5045 AM
X5045 Z AM
AEV
DCB
AEW
DBX
X5045V AM
X5045V Z AM
X5045P
X5045P Z
X5045P I
X5045P Z I
X5045
X5045 Z
X5045 I
X5045 Z I
AEX
DBY
AEY
DBT
X5045V I
X5045V Z I
4.25-4.5
V
CC
RANGE
4.5-5.5V
V
TRIP
RANGE
4.5-4.75
TEMP
RANGE
(°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PACKAGE
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
X5043P Z AL X5045PZ-4.5A (Note) X5045P Z AL
X5043PIZ-4.5A (Note) X5043P Z AM X5045PIZ-4.5A (Note) X5045P Z AM
X5043S8Z-4.5A (Note) X5043 Z AL
X5043S8I-4.5A*
X5043S8IZ-4.5A*
(Note)
X5043M8-4.5A
X5043M8Z-4.5A
(Note)
X5043M8I-4.5A
X5043M8IZ-4.5A
(Note)
X5043V14I-4.5A
X5043V14IZ-4.5A
(Note)
X5043P
X5043PZ (Note)
X5043PI
X5043PIZ (Note)
X5043S8*
X5043S8Z* (Note)
X5043S8I*
X5043S8IZ* (Note)
X5043M8
X5043M8Z (Note)
X5043M8I
X5043M8IZ (Note)
X5043V14I
X5043V14IZ (Note)
X5043 AM
X5043 Z AM
AEM
DBS
AEN
DBM
X5043V AM
X5043V Z AM X5045V14IZ-4.5A
(Note)
X5043P
X5043P Z
X5043P I
X5043P Z I
X5043
X5043 Z
X5043 I
X5043 Z I
AEO
DBN
AEP
DBJ
X5043V I
X5043V Z I
X5045P
X5045PZ (Note)
X5045PI
X5045PIZ (Note)
X5045S8*
X5045S8Z* (Note)
X5045S8I*
X5045S8IZ* (Note)
X5045M8
X5045M8Z (Note)
X5045M8I
X5045M8IZ (Note)
X5045V14I
X5045V14IZ (Note)
3
FN8126.2
March 16, 2006
X5043, X5045
Ordering Information
(Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5043P-2.7A
X5043PZ-2.7A (Note)
X5043PI-2.7A
X5043S8-2.7A*
X5043S8Z-2.7A*
(Note)
X5043S8I-2.7A*
X5043S8IZ-2.7A*
(Note)
X5043M8-2.7A*
X5043M8Z-2.7A
(Note)
X5043M8I-2.7A*
X5043M8IZ-2.7A*
(Note)
X5043V14I-2.7A
X5043V14IZ-2.7A
(Note)
X5043P-2.7
X5043PZ-2.7 (Note)
X5043PI-2.7
X5043PIZ-2.7 (Note)
X5043S8-2.7*
X5043S8I-2.7*
PART
MARKING
X5043P AN
X5043P AP
X5043 AN
X5043 Z AN
X5043 AP
X5043 Z AP
AEQ
DBR
AER
DBL
X5043V AP
PART NUMBER
RESET
(ACTIVE HIGH)
X5045P-2.7A
X5045PI-2.7A
X5045S8-2.7A
X5045S8Z-2.7A
(Note)
X5045S8I-2.7A
X5045S8IZ-2.7A
(Note)
X5045M8-2.7A
X5045M8Z-2.7A
(Note)
X5045M8I-2.7A
X5045M8IZ-2.7A
(Note)
X5045V14I-2.7A
PART
MARKING
X5045P AN
X5045P AP
X5045 AN
X5045 Z AN
X5045 AP
X5045 Z AP
AEZ
DCA
AFA
DBW
X5045V AP
X5045V Z AP
X5045P F
X5045P Z F
X5045P G
X5045P Z G
X5045 F
X5045 G
X5045 Z G
AFB
AFC
2.55-2.7
V
CC
RANGE
2.7-5.5V
V
TRIP
RANGE
2.85-3.0
TEMP
RANGE
(°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
PACKAGE
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC
(Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld PDIP
8 Ld PDIP (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
8 Ld MSOP
8 Ld MSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
X5043P Z AN X5045PZ-2.7A (Note) X5045P Z AN
X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5045P Z AP
X5043V Z AP X5045V14IZ-2.7A
(Note)
X5043P F
X5043P Z F
X5043P G
X5043P Z G
X5043 F
X5043 G
X5045P-2.7
X5045PZ-2.7 (Note)
X5045PI-2.7
X5045PIZ-2.7 (Note)
X5045S8-2.7*
X5045S8I-2.7*
X5045S8IZ-2.7*
(Note)
X5045M8-2.7
X5045M8I-2.7
X5043S8Z-2.7* (Note) X5043 Z F
X5043S8IZ-2.7* (Note) X5043 Z G
X5043M8-2.7
X5043M8Z-2.7 (Note)
X5043M8I-2.7*
X5043M8IZ-2.7*
(Note)
X5043V14I-2.7
X5043V14IZ-2.7
(Note)
AES
DBP
AET
DBK
X5043V G
X5043V Z G
X5045S8Z-2.7* (Note) X5045 Z F
X5045M8Z-2.7 (Note) DBZ
X5045M8IZ-2.7 (Note) DBU
X5045V14I-2.7
X5045V14IZ-2.7
(Note)
X5045V G
X5045V Z G
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4
FN8126.2
March 16, 2006
X5043, X5045
Pin Configuration
8 Ld SOIC/PDIP/MSOP
CS/WDI
SO
WP
V
SS
1
2
3
4
8
7
X5043, X5045
6
5
V
CC
RESET/RESET
SCK
SI
cycle has already been initiated, WP going low will have no
affect on a write.
Reset (RESET, RESET)
X5043, X5045, RESET/RESET is an active low/HIGH, open
drain output which goes active whenever V
CC
falls below the
minimum V
CC
sense level. It will remain active until V
CC
rises above the minimum V
CC
sense level for 200ms.
RESET/RESET also goes active if the Watchdog timer is
enabled and CS remains either high or low longer than the
Watchdog time out period. A falling edge of CS will reset the
watchdog timer.
14 Ld TSSOP
CS
SO
NC
NC
NC
WP
V
SS
1
2
3
4
5
6
7
14
13
12
X5043, X5045
11
10
9
8
V
CC
RESET/RESET
NC
NC
NC
SCK
SI
Pin Names
SYMBOL
CS/WDI
SO
SI
SCK
WP
DESCRIPTION
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Reset Output
Pin Descriptions
Serial Output (SO)
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the
falling edge of the serial clock.
V
SS
V
CC
RESET/RESET
Principles of Operation
Power-on Reset
Application of power to the X5043, X5045 activate a Power-
on Reset Circuit. This circuit pulls the RESET/RESET pin
active. RESET/RESET prevents the system microprocessor
from starting to operate with insufficient voltage or prior to
stabilization of the oscillator. When V
CC
exceeds the device
V
TRIP
value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin executing
code.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input
and output. Opcodes, addresses, or data present on the SI
pin is latched on the rising edge of the clock input, while data
on the SO pin changes after the falling edge of the clock
input.
Low Voltage Monitoring
During operation, the X5043, X5045 monitor the V
CC
level
and asserts RESET/RESET if supply voltage falls below a
preset minimum V
TRIP
. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until V
CC
returns and exceeds V
TRIP
for 200ms.
Chip Select (CS/WDI)
When CS is high, the X5043, X5045 are deselected and the
SO output pin is at high impedance and, unless an internal
write operation is underway, the X5043, X5045 will be in the
standby power mode. CS low enables the X5043, X5045,
placing it in the active power mode. It should be noted that
after power-up, a high to low transition on CS is required prior
to the start of any operation.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent an active
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the Status Register determines the watchdog timer period.
The microprocessor can change these watchdog bits. With
FN8126.2
March 16, 2006
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043, X5045 are
disabled, but the part otherwise functions normally. When
WP is held high, all functions, including non volatile writes
operate normally. WP going low while CS is still low will
interrupt a write to the X5043, X5045. If the internal write
5
嵌入式系统
