®
X5323, X5325
(Replaces X25323, X25325)
Data Sheet
June 30, 2008
FN8131.2
CPU Supervisor with 32kBit SPI EEPROM
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
The device’s low V
CC
detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V
CC
falls below the minimum V
CC
trip point.
RESET/RESET is asserted until V
CC
returns to proper
operating level and stabilizes. Five industry standard V
TRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
Features
• Selectable watchdog timer
• Low V
CC
detection and reset assertion
- Five standard reset threshold voltages
- Re-program low V
CC
reset threshold voltage using
special programming sequence
- Reset signal valid to V
CC
= 1V
• Determine watchdog or low voltage reset with a volatile
flag bit
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 32kbits of EEPROM
• Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock
™
protection
- In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 and 1,1)
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free (RoHS compliant)
Block Diagram
WATCHDOG TRANSITION
DETECTOR
WP
SI
SO
SCK
CS/WDI
DATA
REGISTER
COMMAND
DECODE AND
CONTROL
LOGIC
V
CC
THRESHOLD
RESET LOGIC
PROTECT LOGIC
RESET/RESET
STATUS
REGISTER
8kBITS
8kBITS
16kBITS
EEPROM ARRAY
RESET AND
WATCHDOG
TIMEBASE
X5323 = RESET
X5325 = RESET
WATCHDOG
TIMER RESET
V
CC
V
TRIP
+
-
POWER-ON AND
LOW VOLTAGE
RESET
GENERATION
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X5323, X5325
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
X5323P-4.5A
X5323PZ-4.5A (Note)
X5323PI-4.5A
PART
MARKING
X5323P AL
X5323P ZAL
X5323P AM
PART NUMBER
RESET
(ACTIVE HIGH)
X5325P-4.5A
X5325PZ-4.5A
X5325PI-4.5A
PART
MARKING
X5325P AL
X5325P ZAL
X5325P AM
X5325P ZAM
X5325 AL
V
CC
RANGE
TEMP
(V)
V
TRIP
RANGE RANGE (°C)
4.5 to 5.5
4.5 to 4.75
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
4.5 to 5.5
4.25 to 4.5
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
2.7 to 5.5
2.85 to 3.0
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
X5323PIZ-4.5A (Note) X5323P ZAM X5325PIZ-4.5A
X5323S8-4.5A
X5323 AL
X5325S8-4.5A
X5323S8Z-4.5A (Note) X5323 ZAL
X5323S8I-4.5A*
X5323S8IZ-4.5A*
(Note)
X5323V14-4.5A
X5323V14Z-4.5A
(Note)
X5323V14I-4.5A
X5323V14IZ-4.5A
(Note)
X5323P
X5323PZ (Note)
X5323PI
X5323PIZ (Note)
X5323S8*
X5323S8Z* (Note)
X5323S8I*
X5323S8IZ* (Note)
X5323V14*
X5323V14Z* (Note)
X5323V14I*
X5323V14IZ* (Note)
X5323P-2.7A
X5323PZ-2.7A (Note)
X5323PI-2.7A
X5323 AM
X5323 ZAM
X5323 VAL
X5323 VZAL
X5323 VAM
X5325S8Z-4.5A (Note) X5325 ZAL
X5325S8I-4.5A
X5325S8IZ-4.5A
(Note)
X5325V14-4.5A
X5325V14Z-4.5A
(Note)
X5325V14I-4.5A
X5325 AM
X5325 ZAM
X5325 VAL
X5325 VZAL
X5325 VAM
X5325 VZAM
X5325P
X5325P Z
X5325P I
X5325P ZI
X5325
X5325 Z
X5325 I
X5325 ZI
X5325 V
X5325 VZ
X5325 VI
X5325 VZI
X5325P AN
X5325P ZAN
X5325P AP
X5325P ZAP
X5325 AN
X5323 VZAM X5325V14IZ-4.5A
(Note)
X5323P
X5323P Z
X5323P I
X5323P ZI
X5323
X5323 Z
X5323 I
X5323 ZI
X5323 V
X5323 VZ
X5323 VI
X5323 VZI
X5323P AN
X5325P
X5325PZ
X5325PI
X5325PIZ
X5325S8*
X5325S8Z* (Note)
X5325S8I*
X5325S8IZ* (Note)
X5325V14*
X5325V14Z* (Note)
X5325V14I*
X5325V14IZ* (Note)
X5325P-2.7A
X5323P ZAN X5325PZ-2.7A
X5323P AP
X5325PI-2.7A
X5323PIZ-2.7A (Note) X5323P ZAP X5325PIZ-2.7A
X5323S8-2.7A*
X5323S8Z-2.7A*
(Note)
X5323S8I-2.7A*
X5323S8IZ-2.7A*
(Note)
X5323 AN
X5323 ZAN
X5323 AP
X5323 ZAP
X5325S8-2.7A
X5325S8Z-2.7A (Note) X5325 ZAN
X5325S8I-2.7A
X5325S8IZ-2.7A
(Note)
X5325 AP
X5325 ZAP
2
FN8131.2
June 30, 2008
X5323, X5325
Ordering Information
(Continued)
PART NUMBER
RESET
(ACTIVE LOW)
X5323V14-2.7A
X5323V14Z-2.7A
(Note)
X5323V14I-2.7A
X5323V14IZ-2.7A
(Note)
X5323P-2.7
X5323PZ-2.7 (Note)
X5323PI-2.7
X5323PIZ-2.7 (Note)
X5323S8-2.7*
PART
MARKING
X5323 VAN
PART NUMBER
RESET
(ACTIVE HIGH)
X5325V14-2.7A
PART
MARKING
X5325 VAN
X5325 VZAN
X5325 VAP
X5325 VZAP
X5325P F
X5325P ZF
X5325P G
X5325P ZG
X5325 F
2.7 to 5.5
2.55 to 2.7
V
CC
RANGE
TEMP
(V)
V
TRIP
RANGE RANGE (°C)
2.7 to 5.5
2.85 to 3.0
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
PACKAGE
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld PDIP
8 Ld PDIP** (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
8 Ld SOIC
8 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
14 Ld TSSOP
14 Ld TSSOP
(Pb-free)
X5323 VZAN X5325V14Z-2.7A
(Note)
X5323 VAP
X5325V14I-2.7A
X5323 VZAP X5325V14IZ-2.7A
(Note)
X5323P F
X5323P ZF
X5323P G
X5323P ZG
X5323 F
X5325P-2.7
X5325PZ-2.7
X5325PI-2.7
X5325PIZ-2.7
X5325S8-2.7*
X5323S8Z-2.7* (Note) X5323 ZF
X5323S8I-2.7*
X5323 G
X5325S8Z-2.7* (Note) X5325 ZF
X5325S8I-2.7*
X5325 G
X5323S8IZ-2.7* (Note) X5323 ZG
X5323V14-2.7*
X5323V14Z-2.7*
(Note)
X5323V14I-2.7*
X5323V14IZ-2.7*
(Note)
X5323 VF
X5323 VZF
X5323 VG
X5323 VZG
X5325S8IZ-2.7* (Note) X5325 ZG
X5325V14-2.7*
X5325V14Z-2.7*
(Note)
X5325V14I-2.7*
X5325V14IZ-2.7*
(Note)
X5325 VF
X5325 VZF
X5325 VG
X5325 VZG
*Add “-T1” for tape and reel. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
Pinouts
X5323, X5325
(8 LD SOIC, PDIP)
TOP VIEW
CS/WDI
SO
WP
V
SS
1
2
3
4
8
7
6
5
V
CC
RESET/RESET
SCK
SI
CS/WDI
SO
NC
NC
NC
WP
V
SS
X5323, X5325
(14 LD TSSOP)
TOP VIEW
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
RESET/RESET
NC
NC
NC
SCK
SI
3
FN8131.2
June 30, 2008
X5323, X5325
Pin Descriptions
PIN NUMBER
(SOIC/PDIP)
1
PIN NUMBER
TSSOP
1
PIN NAME
CS/WDI
PIN FUNCTION
Chip Select Input.
CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input.
A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
Serial Output.
SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input.
SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
Serial Clock.
The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect.
The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
Ground
Supply Voltage
Reset Output.
RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever V
CC
falls below the minimum V
CC
sense level. It will remain active until V
CC
rises above
the minimum V
CC
sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
No internal connections
2
5
2
8
SO
SI
6
9
SCK
3
4
8
7
6
7
14
13
WP
V
SS
V
CC
RESET/
RESET
3 to 5,10 to 12
NC
4
FN8131.2
June 30, 2008
X5323, X5325
Principles of Operation
Power-on Reset
Application of power to the X5323/X5325 activates a
power-on reset circuit. This circuit goes active at about 1V
and pulls the RESET/RESET pin active. This signal prevents
the system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscillator. As
long as RESET/RESET pin is active, the device will not
respond to any Read/Write instruction. When V
CC
exceeds
the device V
TRIP
value for 200ms (nominal) the circuit
releases RESET/RESET, allowing the processor to begin
executing code.
To set the new V
TRIP
voltage, apply the desired V
TRIP
threshold to the VCC pin and tie the CS/WDI pin and the WP
pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming voltage V
P
to
both SCK and SI and pulse CS/WDI LOW then HIGH.
Remove V
P
and the sequence is complete.
CS
V
P
SCK
V
P
SI
Low Voltage Monitoring
During operation, the X5323/X5325 monitors the V
CC
level
and asserts RESET/RESET if supply voltage falls below a
preset minimum V
TRIP
. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or
brown-out condition. The RESET/RESET signal remains
active until the voltage drops below 1V. It also remains active
until V
CC
returns and exceeds V
TRIP
for 200ms.
FIGURE 1. SET V
TRIP
VOLTAGE
Resetting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a “native” voltage level. For
example, if the current V
TRIP
is 4.4V and the V
TRIP
is reset,
the new V
TRIP
is something less than 1.7V. This procedure
must be used to set the voltage to a lower value.
To reset the V
TRIP
voltage, apply a voltage between 2.7V
and 5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin,
and the SCK pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming voltage V
P
to the
SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove
V
P
and the sequence is complete.
CS
V
CC
Watchdog Timer
The watchdog timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor must
toggle the CS/WDI pin periodically to prevent a
RESET/RESET signal. The CS/WDI pin must be toggled
from HIGH to LOW prior to the expiration of the watchdog
time out period. The state of two nonvolatile control bits in
the status register determine the watchdog timer period. The
microprocessor can change these watchdog bits, or they
may be “locked” by tying the WP pin LOW and setting the
WPEN bit HIGH.
SCK
V
CC
Threshold Reset Procedure
The X5323/X5325 has a standard V
CC
threshold (V
TRIP
)
voltage. This value will not change over normal operating
and storage conditions. However, in applications where the
standard V
TRIP
is not exactly right, or for higher precision in
the V
TRIP
value, the X5323/X5325 threshold may be
adjusted.
SI
V
P
FIGURE 2. RESET V
TRIP
VOLTAGE
Setting the V
TRIP
Voltage
This procedure sets the V
TRIP
to a higher voltage value. For
example, if the current V
TRIP
is 4.4V and the new V
TRIP
is
4.6V, this procedure directly makes the change. If the new
setting is lower than the current setting, then it is necessary
to reset the trip point before setting the new value.
5
FN8131.2
June 30, 2008
嵌入式系统
