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PPLICATION

OTES AND

EVELOPMENT

YSTEM

A V A I L A B L E

AN20 • AN42–48 • AN50–53 • AN73 • XK9241

Terminal Voltage

5V, 64 Taps

X9241

Quad E

POT

™

Nonvolatile Digital Potentiometer

FEATURES

DESCRIPTION

The X9241 integrates four nonvolatile E

POT digitally

controlled potentiometers on a monolithic CMOS micro-

circuit.

The X9241 contains four resistor arrays, each com-

posed of 63 resistive elements. Between each element

and at either end are tap points accessible to the wiper

elements. The position of the wiper element on the array

is controlled by the user through the two-wire serial bus

interface.

Each resistor array has associated with it a wiper counter

written and read by the user. The contents of the wiper

counter register control the position of the wiper on the

resistor array.

The data register may be read or written by the user. The

contents of the data registers can be transferred to the

wiper counter register to position the wiper. The current

wiper position can be transferred to any one of its

associated data registers.

The arrays may be cascaded to form resistive elements

with 127, 190 or 253 taps.

•

Four E

POTs in One Package

Two-Wire Serial Interface

—Directly Write Wiper Position

—Read Wiper Position

—Store as Many as Four Positions per Pot

Instruction Format

—Quick Transfer of Register Contents to

Resistor Array

—Cascade Resistor Arrays

Low Power CMOS

Direct Write Cell

—Endurance - 100,000 Data Changes per Register

—Register Data Retention - 100 years

16 Bytes of E

PROM memory

3 Resistor Array Values

—2K

Ω

to 50K

Ω

Mask Programmable

—Cascadable For Values of 500

Ω

to 200K

Ω

Resolution: 64 Taps each Pot

20-Lead Plastic DIP, 20-Lead TSSOP and

20-Lead SOIC Packages

FUNCTIONAL DIAGRAM

VH2

WIPER RESISTOR

COUNTER ARRAY

POT 2

(WCR)

R0 R1

WIPER

COUNTER

(WCR)

R2 R3

SCL

SDA

VH0

R0 R1

VL0

VW0

R2 R3

VL2

VW2

INTERFACE

AND

CONTROL

CIRCUITRY

DATA

R0 R1

VH1

WIPER

COUNTER RESISTOR

ARRAY

POT 1

(WCR)

R0 R1

VH3

WIPER

RESISTOR

COUNTER

ARRAY

POT 3

(WCR)

R2 R3

VL1

VW1

R2 R3

VL3

VW3

3864 ILL F07.1

3864-2.7 7/1/96 T0/C3/D3 NS

Characteristics subject to change without notice

X9241

PIN DESCRIPTIONS

PIN NAMES

Symbol

SCL

SDA

A0–A3

–V

H3,

–V

Description

Serial Clock

Serial Data

Address

Potentiometers

(terminal equivalent)

Potentiometers

(wiper equivalent)

3864 PGM T01

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the

X9241.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into and

out of the device. It is an open drain output and may be

wire-ORed with any number of open drain or open

collector outputs. An open drain output requires the use

of a pull-up resistor. For selecting typical values, refer

to the guidelines for calculating typical values on the

bus pull-up resistors graph.

Address

The Address inputs are used to set the least significant

4 bits of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

Address input in order to initiate communication with the

X9241.

PRINCIPLES OF OPERATION

The X9241 is a highly integrated microcircuit incorporat-

ing four resistor arrays, their associated registers and

counters and the serial interface logic providing direct

communication between the host and the E

POT poten-

tiometers.

Serial Interface

The X9241 supports a bidirectional bus oriented proto-

col. The protocol defines any device that sends data

onto the bus as a transmitter and the receiving device as

the receiver. The device controlling the transfer is a

master and the device being controlled is the slave. The

master will always initiate data transfers and provide the

clock for both transmit and receive operations. There-

fore, the X9241 will be considered a slave device in all

applications.

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop

conditions.

Start Condition

Potentiometer Pins

– V

), V

– V

)

The VH and VL inputs are equivalent to the terminal

connections on either end of a mechanical potentiom-

eter.

– V

)

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

PIN CONFIGURATION

DIP/SOIC/TSSOP

VW0

VL0

VH0

VW1

VL1

VH1

SDA

VSS

X9241

VCC

VW3

VL3

VH3

SCL

VW2

VL2

VH2

3864 ILL F01A.2

All commands to the X9241 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH (t

HIGH

). The X9241 continuously

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this condition

is met.

Stop Condition

All communications must be terminated by a stop con-

dition, which is a LOW to HIGH transition of SDA while

SCL is HIGH.

X9241

Acknowledge

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW to

acknowledge that it successfully received the eight bits

of data. See Figure 7.

The X9241 will respond with an acknowledge after

recognition of a start condition and its slave address and

once again after successful receipt of the command

byte. If the command is followed by a data byte the

X9241 will respond with a final acknowledge.

Array Description

The X9241 is comprised of four resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array are

equivalent to the fixed terminals of a mechanical poten-

tiometer (V

and V

inputs).

At both ends of each array and between each resistor

segment is a FET switch connected to the wiper (V

)

output. Within each individual array only one switch may

be turned on at a time. These switches are controlled by

the Wiper Counter Register (WCR). The six least signifi-

cant bits of the WCR are decoded to select, and enable,

one of sixty-four switches.

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

data registers into the WCR. These data registers and

the WCR can be read and written by the host system.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most significant

four bits of the slave address are the device type

identifier (refer to Figure 1 below). For the X9241 this is

fixed as 0101[B].

Figure 1. Slave Address

DEVICE TYPE

IDENTIFIER

PROCEED

3864 ILL F01

The next four bits of the slave address are the device

address. The physical device address is defined by the

state of the A0-A3 inputs. The X9241 compares the

serial data stream with the address input state; a suc-

cessful compare of all four address bits is required for

the X9241 to respond with an acknowledge.

Acknowledge Polling

The disabling of the inputs, during the internal non-

volatile write operation, can be used to take advantage

of the typical 5ms E

PROM write cycle time. Once the

stop condition is issued to indicate the end of the

nonvolatile write command the X9241 initiates the inter-

nal write cycle. ACK polling can be initiated immediately.

This involves issuing the start condition followed by the

device slave address. If the X9241 is still busy with the

write operation no ACK will be returned. If the X9241 has

completed the write operation an ACK will be returned

and the master can then proceed with the next

operation.

Flow 1. ACK Polling Sequence

NONVOLATILE WRITE

COMMAND COMPLETED

ENTER ACK POLLING

ISSUE

START

ISSUE SLAVE

ADDRESS

ISSUE STOP

ACK

RETURNED?

YES

FURTHER

OPERATION?

YES

ISSUE

INSTRUCTION

ISSUE STOP

DEVICE ADDRESS

3864 FHD F08

X9241

Instruction Structure

The next byte sent to the X9241 contains the instruction

and register pointer information. The four most signifi-

cant bits are the instruction. The next four bits point to

one of four pots and when applicable they point to one

of four associated registers. The format is shown below

in Figure 2.

Figure 2. Instruction Byte Format

POTENTIOMETER

SELECT

action will be delayed t

STPWV

. A transfer from WCR

current wiper position, to a data register is a write to

nonvolatile memory and takes a minimum of t

complete. The transfer can occur between one of the

four potentiometers and one of its associated registers;

or it may occur globally, wherein the transfer occurs

between all four of the potentiometers and one of their

associated registers.

Four instructions require a three-byte sequence to

complete. These instructions transfer data between the

host and the X9241; either between the host and one of

the data registers or directly between the host and the

WCR. These instructions are: Read WCR, read the

current wiper position of the selected pot; Write WCR,

change current wiper position of the selected pot; Read

Data Register, read the contents of the selected non-

volatile register; Write Data Register, write a new value

to the selected data register. The sequence of opera-

tions is shown in Figure 4.

The Increment/Decrement command is different from

the other commands. Once the command is issued and

the X9241 has responded with an acknowledge, the

master can clock the selected wiper up and/or down in

one segment steps; thereby, providing a fine tuning

capability to the host. For each SCL clock pulse (t

HIGH

)

while SDA is HIGH, the selected wiper will move one

resistor segment towards the V

terminal. Similarly, for

each SCL clock pulse while SDA is LOW, the selected

wiper will move one resistor segment towards the V

terminal. A detailed illustration of the sequence and

timing for this operation are shown in Figures 5 and 6

respectively.

INSTRUCTIONS

SELECT

3864 ILL F09.1

The four high order bits define the instruction. The next

two bits (P1 and P0) select which one of the four

potentiometers is to be affected by the instruction. The

last two bits (R1 and R0) select one of the four registers

that is to be acted upon when a register oriented instruc-

tion is issued.

Four of the nine instructions end with the transmission of

the instruction byte. The basic sequence is illustrated in

Figure 3. These two-byte instructions exchange data

between the WCR and one of the data registers. A

transfer from a data register to a WCR is essentially a

write to a static RAM. The response of the wiper to this

Figure 3. Two-Byte Command Sequence

SCL

SDA

P1 P0

R1 R0

3864 ILL F10

X9241

Figure 4. Three-Byte Command Sequence

SCL

SDA

P1 P0

R1 R0

CM DW D5 D4 D3

D1 D0

3864 ILL F11

Figure 5. Increment/Decrement Command Sequence

SCL

SDA

P1 P0

R1 R0

3864 FHD F12

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

ISSUED

SCL

tCLWV

SDA

VOLTAGE OUT

3864 ILL F13