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PPLICATION

OTE

A V A I L A B L E

AN20 • AN42–48 • AN50-53 • AN73 • AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135

Low Power/2-Wire Serial Bus

X9241A

Quad Digitally Controlled Potentiometer (XDCP

™

)

FEATURES

• Four potentiometers in one package

• 2-wire serial interface

• Register oriented format

—Direct read/write/transfer of wiper positions

—Store as many as four positions per

potentiometer

• Terminal Voltages: +5V, -3.0V

• Cascade resistor arrays

• Low power CMOS

• High Reliability

—Endurance–100,000 data changes per bit per

—Register data retention–100 years

• 16-bytes of nonvolatile memory

• 3 resistor array values

—2K

Ω

to 50K

Ω

mask programmable

—Cascadable for values of 500

Ω

to 200K

Ω

• Resolution: 64 taps each pot

• 20-lead plastic DIP, 20-lead TSSOP and 20-lead

SOIC packages

DESCRIPTION

The X9241A integrates four digitally controlled

potentiometers (XDCP) on a monolithic CMOS

integrated microcircuit.

The digitally controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the 2-wire

bus interface. Each potentiometer has associated with

it a volatile Wiper Counter Register (WCR) and 4

nonvolatile Data Registers (DR0:DR3) that can be

directly written to and read by the user. The contents

of the WCR controls the position of the wiper on the

resistor array through the switches. Power up recalls

the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal

potentiometer or as a two-terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

BLOCK DIAGRAM

R0 R1

Wiper

Counter

(WCR)

R0 R1

Wiper

Counter

(WCR)

Array

Pot 2

R2 R3

SCL

SDA

R2 R3

Interface

and

Control

Circuitry

Data

R0 R1

Wiper

Counter

(WCR)

Array

Pot 1

R0 R1

Wiper

Counter

(WCR)

Array

Pot 3

R2 R3

REV 1.1.13 12/09/02

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Characteristics subject to change without notice.

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X9241A

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

The SCL input is used to clock data into and out of the

X9241A.

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into

and out of the device. It is an open drain output and

may be wire-ORed with any number of open drain or

open collector outputs. An open drain output requires

the use of a pull-up resistor. For selecting typical

values, refer to the guidelines for calculating typical

values on the bus pull-up resistors graph.

Address

The Address inputs are used to set the least

signiﬁcant 4 bits of the 8-bit slave address. A match in

the slave address serial data stream must be made

with the Address input in order to initiate

communication with the X9241A.

Potentiometer Pins

—V

), V

—V

)

The R

and R

inputs are equivalent to the terminal

connections on either end of a mechanical

potentiometer.

—V

)

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

SDA

PIN CONFIGURATION

DIP/SOIC/TSSOP

X9241A

SCL

PIN NAMES

Symbol

SCL

SDA

A0–A3

–V

Description

Serial Clock

Serial Data

Address

Potentiometer Pins

(terminal equivalent)

Potentiometer Pins

(wiper equivalent)

PRINCIPLES OF OPERATION

The X9241A is a highly integrated microcircuit

incorporating four resistor arrays, their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

REV 1.1.13 12/09/02

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Characteristics subject to change without notice.

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X9241A

Serial Interface

The X9241A supports a bidirectional bus oriented

protocol. The protocol deﬁnes any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9241A will be considered a

slave device in all applications.

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW periods (t

LOW

). SDA state changes during

SCL HIGH are reserved for indicating start and stop

conditions.

Start Condition

All commands to the X9241A are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH (t

HIGH

). The X9241A continuously

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this

condition is met.

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH.

Acknowledge

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data. See Figure 7.

The X9241A will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9241A will respond with a ﬁnal acknowledge.

Array Description

The X9241A is comprised of four resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the ﬁxed terminals of a mechanical

potentiometer (V

and V

inputs).

At both ends of each array and between each resistor

segment is a FET switch connected to the wiper (V

) output. Within each individual array only one

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

six least signiﬁcant bits of the WCR are decoded to

select, and enable, one of sixty-four switches.

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

Data Registers into the WCR. These Data Registers

and the WCR can be read and written by the host

system.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most

signiﬁcant four bits of the slave address are the device

type identiﬁer (refer to Figure 1 below). For the X9241A

this is ﬁxed as 0101[B].

Figure 1. Slave Address

Device Type

Identifier

Device Address

The next four bits of the slave address are the device

address. The physical device address is deﬁned by the

state of the A0-A3 inputs. The X9241A compares the

serial data stream with the address input state; a

successful compare of all four address bits is required

for the X9241A to respond with an acknowledge.

REV 1.1.13 12/09/02

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Characteristics subject to change without notice.

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X9241A

Acknowledge Polling

The disabling of the inputs, during the internal

nonvolatile write operation, can be used to take

advantage of the typical 5ms EEPROM write cycle

time. Once the stop condition is issued to indicate the

end of the nonvolatile write command the X9241A

initiates the internal write cycle. ACK polling can be

initiated immediately. This involves issuing the start

condition followed by the device slave address. If the

X9241A is still busy with the write operation no ACK

will be returned. If the X9241A has completed the

write operation an ACK will be returned and the

master can then proceed with the next operation.

Flow 1. ACK Polling Sequence

Instructions

Nonvolatile Write

Command Completed

Enter ACK Polling

Select

Instruction Structure

The next byte sent to the X9241A contains the

instruction and register pointer information. The four

most signiﬁcant bits are the instruction. The next four

bits point to one of four pots and when applicable they

point to one of four associated registers. The format is

shown below in Figure 2.

Figure 2. Instruction Byte Format

Potentiometer

Select

Issue

START

The four high order bits deﬁne the instruction. The next

two bits (P1 and P0) select which one of the four

potentiometers is to be affected by the instruction. The

last two bits (R1 and R0) select one of the four

registers that is to be acted upon when a register

oriented instruction is issued.

Issue STOP

Issue Slave

Address

ACK

Returned?

Yes

FurTher

OperaTion?

Yes

Issue

Instruction

Issue STOP

Four of the nine instructions end with the transmission

of the instruction byte. The basic sequence is

illustrated in Figure 3. These two-byte instructions

exchange data between the WCR and one of the data

registers. A transfer from a Data Register to a WCR is

essentially a write to a static RAM. The response of

the wiper to this action will be delayed t

STPWV

. A

transfer from WCR current wiper position, to a Data

minimum of t

to complete. The transfer can occur

between one of the four potentiometers and one of its

associated registers; or it may occur globally, wherein

the transfer occurs between all four of the

potentiometers and one of their associated registers.

Four instructions require a three-byte sequence to

complete. These instructions transfer data between

the host and the X9241A; either between the host and

one of the Data Registers or directly between the host

and the WCR. These instructions are: Read WCR,

read the current wiper position of the selected pot;

Write WCR, change current wiper position of the

selected pot; Read Data Register, read the contents of

the selected nonvolatile register; Write Data Register,

write a new value to the selected Data Register. The

sequence of operations is shown in Figure 4.

Proceed

REV 1.1.13 12/09/02

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Characteristics subject to change without notice.

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X9241A

The Increment/Decrement command is different from

the other commands. Once the command is issued and

the X9241A has responded with an acknowledge, the

master can clock the selected wiper up and/or down in

one segment steps; thereby, providing a ﬁne tuning

capability to the host. For each SCL clock pulse (t

HIGH

)

while SDA is HIGH, the selected wiper will move one

Figure 3. Two-Byte Instruction Sequence

SCL

resistor segment towards the V

terminal. Similarly,

for each SCL clock pulse while SDA is LOW, the

selected wiper will move one resistor segment towards

the V

terminal. A detailed illustration of the

sequence and timing for this operation are shown in

Figures 5 and 6 respectively.

SDA

P1 P0

R1 R0

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

A3 A2 A1 A0 A

I1 I0

P1 P0 R1 R0

A CM DW D5 D4 D3 D2 D1 D0 A

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

A3 A2 A1 A0

P1 P0 R1 R0

REV 1.1.13 12/09/02

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Characteristics subject to change without notice.

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