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PPLICATION

OTE

A V A I L A B L E

AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135

Low Noise/Low Power/SPI Bus/256 Taps

X9250

Quad Digitally Controlled Potentiometers (XDCP

™

)

FEATURES

•

Four potentiometers in one package

256 resistor taps/pot–0.4% resolution

SPI serial interface

Wiper resistance, 40

Ω

typical @ V

= 5V

Four nonvolatile data registers for each pot

Nonvolatile storage of wiper position

Standby current < 5µA max (total package)

Power supplies

—V

= 2.7V to 5.5V

—V+ = 2.7V to 5.5V

—V– = -2.7V to -5.5V

100K

Ω

, 50K

Ω

total pot resistance

High reliability

—Endurance – 100,000 data changes per bit per

—Register data retention – 100 years

24-lead SOIC, 24-lead TSSOP, 24-lead CSP (Chip

Scale Package)

Dual supply version of X9251

DESCRIPTION

The X9250 integrates 4 digitally controlled

potentiometers (XDCP) on a monolithic CMOS

integrated circuit.

The digitally controlled potentiometer is implemented

using 255 resistive elements in a series array.

Between each element are tap points connected to

the wiper terminal through switches. The position of

the wiper on the array is controlled by the user through

the SPI bus interface. Each potentiometer has

associated with it a volatile Wiper Counter Register

(WCR) and 4 nonvolatile Data Registers (DR0:DR3)

that can be directly written to and read by the user.

The contents of the WCR controls the position of the

wiper on the resistor array though the switches. Power

up recalls the contents of DR0 to the WCR.

The XDCP can be used as a three-terminal

potentiometer or as a two-terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

•

BLOCK DIAGRAM

V+

V-

Wiper

Counter

(WCR)

Pot 0

Wiper

Counter

(WCR)

HOLD

SCK

Resistor

Array

Pot 2

Interface

and

Control

Circuitry

Data

Wiper

Counter

(WCR)

Wiper

Counter

(WCR)

Resistor

Array

Pot1

Resistor

Array

Pot 3

REV 1.2 4/13/04

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Characteristics subject to change without notice.

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X9250

PIN DESCRIPTIONS

Serial Output (SO)

SO is a serial data output pin. During a read cycle,

data is shifted out on this pin. Data is clocked out by

the falling edge of the serial clock.

Serial Input

SI is the serial data input pin. All opcodes, byte

addresses and data to be written to the pots and pot

registers are input on this pin. Data is latched by the

rising edge of the serial clock.

Serial Clock (SCK)

The SCK input is used to clock data into and out of the

X9250.

Chip Select (CS)

When CS is HIGH, the X9250 is deselected and the

SO pin is at high impedance, and (unless an internal

write cycle is underway) the device will be in the

standby state. CS LOW enables the X9250, placing it

in the active power mode. It should be noted that after

a power-up, a HIGH to LOW transition on CS is

required prior to the start of any operation.

Hold (HOLD)

HOLD is used in conjunction with the CS pin to select

the device. Once the part is selected and a serial

sequence is underway, HOLD may be used to pause

the serial communication with the controller without

resetting the serial sequence. To pause, HOLD must

be brought LOW while SCK is LOW. To resume

communication, HOLD is brought HIGH, again while

SCK is LOW. If the pause feature is not used, HOLD

should be held HIGH at all times.

Device Address (A

–

)

The address inputs are used to set the least signiﬁcant

2 bits of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

address input in order to initiate communication with

the X9250. A maximum of 4 devices may occupy the

SPI serial bus.

Potentiometer Pins

–V

), V

–V

)

The R

and R

pins are equivalent to the terminal

connections on a mechanical potentiometer.

REV 1.2 4/13/04

–V

)

The wiper pins are equivalent to the wiper terminal of

a mechanical potentiometer.

Hardware Write Protect Input (WP)

The WP pin when LOW prevents nonvolatile writes to

the Data Registers.

Analog Supplies (V+, V-)

The analog supplies V+, V- are the supply voltages for

the XDCP analog section.

PIN CONFIGURATION

SOIC/TSSOP

V+

X9250

HOLD

SCK

V–

CSP

WP SI

V+ R

V-

SO HOLD R

SCK R

Top View–Bumps Down

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Characteristics subject to change without notice.

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X9250

PIN NAMES

Symbol

SCK

SI, SO

-A

H0–

L0–

W0–

V+,V-

Description

Serial Clock

Serial Data

Device Address

Potentiometer Pins

(terminal equivalent)

Potentiometer Pins

(wiper equivalent)

Hardware Write Protection

Analog Supplies

System Supply Voltage

System Ground

No Connection

Wiper Counter Register (WCR)

The X9250 contains four Wiper Counter Registers,

one for each XDCP potentiometer. The WCR is

equivalent to a serial-in, parallel-out register/counter

with its outputs decoded to select one of 256 switches

along its resistor array. The contents of the WCR can

be altered in four ways: it may be written directly by the

host via the write Wiper Counter Register instruction

(serial load); it may be written indirectly by transferring

the contents of one of four associated Data Registers

via the XFR Data Register or Global XFR Data

one step at a time by the increment/decrement

instruction. Finally, it is loaded with the contents of its

Data Register zero (DR0) upon power-up.

The Wiper Counter Register is a volatile register; that

is, its contents are lost when the X9250 is powered-

down. Although the register is automatically loaded

with the value in R0 upon power-up, this may be

different from the value present at power-down.

Data Registers

Each potentiometer has four 8-bit nonvolatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Counter

Data Registers is a nonvolatile operation and will take

a maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can

be used as regular memory locations for system

parameters or user preference data.

Data Register Detail

(MSB)

(LSB)

DEVICE DESCRIPTION

Serial Interface

The X9250 supports the SPI interface hardware

conventions. The device is accessed via the SI input

with data clocked in on the rising SCK. CS must be

LOW and the HOLD and WP pins must be HIGH

during the entire operation.

The SO and SI pins can be connected together, since

they have three state outputs. This can help to reduce

system pin count.

Array Description

The X9250 is comprised of four resistor arrays. Each

array contains 255 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the ﬁxed terminals of a mechanical

potentiometer (V

and V

inputs).

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

) output. Within each individual array only one

switch may be turned on at a time.

These switches are controlled by a Wiper Counter

to select, and enable, one of 256 switches.

REV 1.2 4/13/04

www.xicor.com

Characteristics subject to change without notice.

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X9250

Figure 1. Detailed Potentiometer Block Diagram

(One of Four Arrays)

Serial Data Path

From Interface

Circuitry

Parallel

Bus

Input

Wiper

Counter

(WCR)

Serial

Bus

Input

If WCR = 00[H] then V

= V

If WCR = FF[H] then V

= V

Inc/Dec

Logic

UP/DN

Modified SCK

UP/DN

CLK

Write in Process

The contents of the Data Registers are saved to

nonvolatile memory when the CS pin goes from LOW

to HIGH after a complete write sequence is received

by the device. The progress of this internal write

operation can be monitored by a write in process bit

(WIP). The WIP bit is read with a read status

command.

INSTRUCTIONS

Identification (ID) Byte

The ﬁrst byte sent to the X9250 from the host,

following a CS going HIGH to LOW, is called the

Identiﬁcation byte. The most signiﬁcant four bits of the

slave address are a device type identiﬁer, for the

X9250 this is ﬁxed as 0101[B] (refer to Figure 2).

The two least signiﬁcant bits in the ID byte select one

of four devices on the bus. The physical device

address is deﬁned by the state of the A

-A

input pins.

The X9250 compares the serial data stream with the

address input state; a successful compare of both

address bits is required for the X9250 to successfully

continue the command sequence. The A

–A

inputs

can be actively driven by CMOS input signals or tied to

or V

The remaining two bits in the slave byte must be set to 0.

REV 1.2 4/13/04

Figure 2. Identification Byte Format

Device Type

Identifier

Device Address

Instruction Byte

The next byte sent to the X9250 contains the

instruction and register pointer information. The four

most signiﬁcant bits are the instruction. The next four

bits point to one of the four pots and, when applicable,

they point to one of four associated registers. The

format is shown below in Figure 3.

Figure 3. Instruction Byte Format

Select

Instructions

Pot Select

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Characteristics subject to change without notice.

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X9250

The four high order bits of the instruction byte specify

the operation. The next two bits (R

and R

) select one

of the four registers that is to be acted upon when a

(P1 and P

) selects which one of the four

potentiometers is to be affected by the instruction.

Four of the ten instructions are two bytes in length and

end with the transmission of the instruction byte. These

instructions are:

– XFR Data Register to Wiper Counter Register—This

transfers the contents of one speciﬁed Data Register

to the associated Wiper Counter Register.

– XFR Wiper Counter Register to Data Register—This

transfers the contents of the speciﬁed Wiper Counter

– Global XFR Data Register to Wiper Counter Register—

This transfers the contents of all speciﬁed Data Reg-

isters to the associated Wiper Counter Registers.

– Global XFR Wiper Counter Register to Data Register—

This transfers the contents of all Wiper Counter Reg-

isters to the speciﬁed associated Data Registers.

The basic sequence of the two byte instructions is

illustrated in Figure 4. These two-byte instructions

exchange data between the WCR and one of the Data

Registers. A transfer from a Data Register to a WCR is

essentially a write to a static RAM, with the static RAM

controlling the wiper position. The response of the wiper

to this action will be delayed by t

WRL

. A transfer from

the WCR (current wiper position), to a Data Register is

a write to nonvolatile memory and takes a minimum of

to complete. The transfer can occur between one of

the four potentiometers and one of its associated

registers; or it may occur globally, where the transfer

occurs between all potentiometers and one associated

Five instructions require a three-byte sequence to

complete. These instructions transfer data between the

host and the X9250; either between the host and one of

the data registers or directly between the host and the

Wiper Counter Register. These instructions are:

– Read Wiper Counter Register—read the current

wiper position of the selected pot,

– Write Wiper Counter Register—change current wiper

position of the selected pot,

– Read Data Register—read the contents of the

selected data register;

– Write Data Register—write a new value to the

selected data register.

– Read Status—This command returns the contents of

the WIP bit which indicates if the internal write cycle

is in progress.

The sequence of these operations is shown in Figure 5

and Figure 6.

The ﬁnal command is Increment/Decrement. It is

different from the other commands, because it’s length

is indeterminate. Once the command is issued, the

master can clock the selected wiper up and/or down in

one resistor segment steps; thereby, providing a ﬁne

tuning capability to the host. For each SCK clock pulse

HIGH

) while SI is HIGH, the selected wiper will move

one resistor segment towards the V

terminal.

Similarly, for each SCK clock pulse while SI is LOW, the

selected wiper will move one resistor segment towards

the V

terminal. A detailed illustration of the sequence

and timing for this operation are shown in Figure 7 and

Figure 8.

REV 1.2 4/13/04

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Characteristics subject to change without notice.

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