DATASHEET
X9400
Low Noise/Low Power/SPI Bus Quad Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Four potentiometers per package
• 64 resistor taps
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40 typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on
power-up.
• Standby current < 1µA max
• System V
CC
: 2.7V to 5.5V operation
• Analog V
+
/V
–
: -5V to +5V
• 10k, 2.5k end to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
• 24 Ld SOIC and 24 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
DESCRIPTION
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power-up recalls the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
FN8189
Rev 4.00
September 2, 2015
BLOCK DIAGRAM
V
CC
V
SS
V+
V-
HOLD
CS
SCK
SO
SI
A0
A1
WP
Interface
and
Control
Circuitry
Data
R0 R1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R0 R1
Pot 0
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
R0 R1
Wiper
Counter
Register
(WCR)
V
H2
/R
H2
R2 R3
V
L0
/R
L0
V
W0
/R
W0
R2 R3
Resistor
Array
Pot 2
V
L2
/R
L2
V
W2
/R
W2
8
V
W1
/R
W1
V
H1
/R
H1
R0 R1
Wiper
Counter
Register
(WCR)
V
W3
/R
W3
V
H3
/R
H3
R2 R3
V
L1
/R
L1
R2 R3
Resistor
Array
Pot 3
V
L3
/R
L3
FN8189 Rev 4.00
September 2, 2015
Page 1 of 20
X9400
Ordering Information
PART NUMBER
PART
MARKING
V
CC
LIMITS
(V)
5 ±10%
POTENTIOMETER
ORGANIZATION
(k)
10
TEMP.
RANGE
(°C)
0 to +70
PACKAGE
PKG.
DWG. #
X9400WS24ZT1 (Note)
(No longer available,
X9400WS Z
recommended replacement: X9400WS24IZT1)
X9400WS24IZ* (Note)
X9400WV24IZ* (Note)
X9400WS ZI
X9400WV ZI
24 Ld SOIC (300 mil)
M24.3
(Pb-free) Tape and Reel
M24.3
MDP0044
MDP0044
M24.3
MDP0044
MDP0044
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
-40 to +85 24 Ld TSSOP (4.4mm)
(Pb-free)
0 to +70
24 Ld TSSOP (4.4mm)
(Pb-free)
X9400WV24Z* (Note)
(No longer available,
X9400WV Z
recommended replacement: X9400WS24IZT1)
X9400WS24IZ-2.7* (Note)
X9400WS ZG 2.7 to 5.5
-40 to +85 24 Ld SOIC (300 mil)
(Pb-free)
-40 to +85 24 Ld TSSOP (4.4mm)
(Pb-free)
0 to +70
24 Ld TSSOP (4.4mm)
(Pb-free)
X9400WV24IZ-2.7* (Note)
(No longer available,
X9400WV ZG
recommended replacement: X9400WS24IZT1)
X9400WV24Z-2.7* (Note)
(No longer available,
X9400WV ZF
recommended replacement: X9400WS24IZT1)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8189 Rev 4.00
September 2, 2015
Page 2 of 20
X9400
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9400.
Chip Select (CS)
When CS is HIGH, the X9400 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby
state. CS LOW enables the X9400, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
PIN CONFIGURATION
SOIC
V
CC
V
L0
/R
L0
V
H0
/R
H0
V
W0
/R
W0
CS
WP
SI
A
1
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
SS
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
Device Address (A
0
-
A
1
)
The address inputs are used to set the least significant 2
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with the
X9400. A maximum of 4 devices may occupy the SPI
serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H3
/R
H3
), V
L
/R
L
(V
L0
/R
L0
- V
L3
/R
L3
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W
/R
W
(V
W0
/R
W0
- V
W3
/R
W3
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Analog Supplies (V+, V-)
The analog Supplies V+, V- are the supply voltages for
the XDCP analog section.
TSSOP
24
23
22
21
20
19
18
17
16
15
14
13
V+
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
A
0
SO
HOLD
SCK
V
L2
/R
L2
V
H2
/R
H2
V
W2
/R
W2
V-
SI
A
1
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
SS
V-
V
W2
/R
W2
V
H2
/R
H2
V
L2
/R
L2
SCK
HOLD
1
2
3
4
5
6
7
8
9
10
11
12
X9400
24
23
22
21
20
19
18
17
16
15
14
13
WP
CS
V
W0
/R
W0
V
H0
/R
H0
V
L0
/R
L0
V
CC
V+
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
A
0
SO
1
2
3
4
5
6
7
8
9
10
11
12
X9400
FN8189 Rev 4.00
September 2, 2015
Page 3 of 20
X9400
PIN NAMES
Symbol
SCK
SI, SO
A
0
- A
1
V
H0
/R
H0
- V
H3
/R
H3
,
V
L0
/R
L0
- V
L3
/R
L3
V
W0
/R
W0
- V
W1
/R
W1
WP
V
CC
V
SS
NC
Wiper Counter Register (WCR)
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins (terminal
equivalent)
Potentiometer Pins (wiper
equivalent)
Hardware Write Protection
System Supply Voltage
System Ground
No Connection
The X9400 contains four Wiper Counter Registers, one
for each XDCP potentiometer. The WCR is equivalent to
a serial-in, parallel-out register/counter with its outputs
decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered
in four ways: it may be written directly by the host via the
write Wiper Counter Register instruction (serial load); it
may be written indirectly by transferring the contents of
one of four associated data registers via the XFR Data
Register or global XFR data register instructions
(parallel load); it can be modified one step at a time by
the increment/decrement instruction. Finally, it is loaded
with the contents of its Data Register zero (DR0) upon
power-up.
The Wiper Counter Register is a volatile register; that is,
its contents are lost when the X9400 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the data
registers is a nonvolatile operation and will take a
maximum of 10ms.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system
parameters or user preference data.
Data Register Detail
(MSB)
D5
NV
D4
NV
D3
NV
D2
NV
D1
NV
(LSB)
D0
NV
DEVICE DESCRIPTION
The X9400 is a highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a wiper counter
register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
FN8189 Rev 4.00
September 2, 2015
Page 4 of 20
X9400
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 1
6
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Serial
Bus
Input
C
o
u
n
t
e
r
D
e
c
o
d
e
V
H
/R
H
Register 2
Register 3
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = 3F[H] then V
W
/R
W
= V
H
/R
H
UP/DN
Modified SCL
INC/DEC
Logic
UP/DN
CLK
V
L
/R
L
V
W
/R
W
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a write in process bit (WIP). The WIP bit
is read with a read status command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9400 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9400 this is fixed as
0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A
0
- A
1
input pins. The X9400
compares the serial data stream with the address input
state; a successful compare of both address bits is
required for the X9400 to successfully continue the
command sequence. The A
0
- A
1
inputs can be actively
driven by CMOS input signals or tied to V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
FN8189 Rev 4.00
September 2, 2015
Figure 2. Identification Byte Format
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9400 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next four bits
point to one of the four pots and, when applicable, they
point to one of four associated registers. The format is
shown below in Figure 3.
Page 5 of 20
FPGA/CPLD
