X9409
OBSOLETE PRODUCT
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN8192
Rev.6.00
Sep 3, 2015
Low Noise/Low Power/2-Wire Bus Quad Digitally Controlled Potentiometers
(XDCP)
The
X9409
integrates 4 digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated microcircuit.
The digitally controlled potentiometer is implemented using
63 resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled by
the user through the 2-wire bus interface. Each potentiometer
has associated with it a volatile Wiper Counter Register (WCR)
and 4 nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of DR0 to
the WCR.
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments and
signal processing.
Features
• Four potentiometers per package
• 64 resistor taps
• 2-wire serial interface for write, read and transfer operations
of the potentiometer
• 50Ω wiper resistance, typical at 5V
• Four nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper position
• Power-on recall. Loads saved wiper position on power-up
standby current < 1µA typical
• System V
CC
: 2.7V operation
• 10kΩ end-to-end resistance
• 100 year data retention
• Endurance: 100,000 data changes per bit per register
• Low power CMOS
• 24 Ld TSSOP
• Pb-free (RoHS compliant)
V
CC
V
SS
R
0
R
1
POT 0
WIPER
COUNTER
REGISTER
(WCR)
V
H0
/R
HO
R
0
R
1
WIPER
COUNTER
REGISTER
(WCR)
V
H2
/R
H2
WP
SCL
SDA
A0
A1
A2
A3
INTERFACE
AND
CONTROL
CIRCUITRY
DATA
R
2
R
3
V
L0
/
R
LO
V
W0
/
R
WO
RESISTOR
ARRAY
POT 2
R
2
R
3
V
L2
/R
L2
V
W2
/R
W2
8
V
W1
/
R
W1
R
0
R
1
WIPER
COUNTER
REGISTER
(WCR)
RESISTOR
ARRAY
POT 1
V
H1
/
R
H1
R
0
R
1
WIPER
COUNTER
REGISTER
(WCR)
V
W3
/R
W3
V
H3
/R
H3
R
2
R
3
V
L1
/R
L1
R
2
R
3
RESISTOR
ARRAY
Pot 3
V
L3
/R
L3
FIGURE 1. BLOCK DIAGRAM
FN8192 Rev.6.00
Sep 3, 2015
Page 1 of 19
X9409
Ordering Information
PART NUMBER
(Notes
1, 2, 3)
PART
MARKING
POTENTIOMETER
TEMP
V
CC
LIMITS ORGANIZATION
(kΩ)
RANGE (°C)
(V)
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
2.7 to 5.5
10
10
10
10
-40 to +85
-40 to +85
-40 to +85
0 to +70
PACKAGE
(RoHS Compliant)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
PKG.
DWG. #
M24.173
M24.173
M24.173
M24.173
X9409WV24IZ (No longer available,
X9409WV ZI
recommended replacement: X9409WV24IZ-2.7)
X9409WV24IZ-2.7
X9409WV ZG
X9409WV24Z (No longer available,
X9409WV Z
recommended replacement: X9409WV24IZ-2.7)
X9409WV24Z-2.7 (No longer available,
X9409WV ZF
recommended replacement: X9409WV24IZ-2.7)
NOTES:
1. Add “T1” suffix for tape and reel. Please refer to
TB347
for details on reel specifications.
2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for
X9409.
For more information on MSL, please see tech brief
TB363.
Pin Configuration
X9409
(24 LD TSSOP)
TOP VIEW
SDA
A
1
V
L1
/R
L1
V
H1
/R
H1
V
W1
/R
W1
V
SS
NC
V
W2
/R
W2
V
H2
/R
H2
V
L2
/R
L2
SCL
A
3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
WP
A
2
V
W0
/R
W0
V
H0
/R
H0
V
L0
/R
L0
V
CC
NC
V
L3
/R
L3
V
H3
/R
H3
V
W3
/R
W3
A
0
NC
Pin Descriptions
PIN #
11
1
14, 2, 23, 12
21, 4, 9, 16, 20, 3, 10, 17
22, 5, 8, 15
24
19
6
7, 13, 18
SCL
SDA
A
0
, A
1
, A
2
, A
3
V
H0
/R
H0
, V
H1
/R
H1
, V
H2
/R
H2
, V
H3
/R
H3
, V
L0
/R
L0
, V
L1
/R
L1
,
V
L2
/R
L2
, V
L3
/R
L3
V
W0
/R
W0
, V
W1
/R
W1
, V
W2
/R
W2
, V
W3
/R
W3
WP
V
CC
V
SS
NC
SYMBOL
Serial Clock
Serial Data
Device Address
Potentiometer Pin (terminal equivalent)
Potentiometer Pin (wiper equivalent)
Hardware Write Protection
System Supply Voltage
System Ground (Digital)
No Connection
DESCRIPTION
FN8192 Rev.6.00
Sep 3, 2015
Page 2 of 19
X9409
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the X9409.
START CONDITION
All commands to the X9409 are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA while SCL is HIGH
(t
HIGH
). The X9409 continuously monitors the SDA and SCL lines
for the start condition and will not respond to any command until
this condition is met.
SERIAL DATA (SDA)
The SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-O Red
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is HIGH.
ACKNOWLEDGE
Acknowledge is a software convention used to provide a positive
handshake between the master and slave devices on the bus to
indicate the successful receipt of data. The transmitting device,
either the master or the slave, will release the SDA bus after
transmitting eight bits. The master generates a ninth clock cycle
and during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits of data.
The X9409 will respond with an acknowledge after recognition of
a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9409 will respond with a final
acknowledge.
DEVICE ADDRESS (A
0
, A
2
, A
3
)
The address inputs are used to set the least significant 4 bits of
the 8-bit slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
communication with the X9409. A maximum of 16 devices may
occupy the 2-wire serial bus.
Potentiometer Pins
V
H0
/R
H0
- V
H3
/R
H3
, V
L0
/R
L0
- V
L3
/R
L3
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
V
W0
/R
W0 -
V
W3
/R
W3
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
ARRAY DESCRIPTION
The X9409 is comprised of four resistor arrays. Each array
contains 63 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (V
W
/R
W
) output. Within
each individual array only one switch may be turned on at a time.
These switches are controlled by the Wiper Counter Register
(WCR). The 6 bits of the WCR are decoded to select and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR can
be read and written by the host system.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
PRINCIPLES OF OPERATION
The X9409 is a highly integrated microcircuit incorporating four
resistor arrays and their associated registers and counters and the
serial interface logic providing direct communication between the
host and the XDCP potentiometers.
Serial Interface
The X9409 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9409 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (t
LOW
). The SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
FN8192 Rev.6.00
Sep 3, 2015
Page 3 of 19
X9409
Symbol Table
WAVEFORM
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
OUTPUTS
Will be
steady
Will change
from Low to
High
Guidelines for Calculating
Typical Values of Bus Pull-Up
Resistors
120
100
RESISTANCE (k)
80
R
MAX =
60
40
20
0
0
20
40
60
80
100
120
BUS CAPACITANCE (pF)
V
CC MAX
I
OL MIN
t
R
C
BUS
MAX.
RESISTANCE
MIN.
RESISTANCE
R
MIN =
= 1.8kΩ
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
FN8192 Rev.6.00
Sep 3, 2015
Page 4 of 19
X9409
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SDA, SCL or any address input with respect to V
SS
.-1V to +7V
V = |V
H
- V
L
| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
ESD Rating
Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . 4kV
Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . 300V
Thermal Information
Thermal Resistance
JA
(°C/W)
JC
(°C/W)
24 Ld TSSOP (Notes
4, 5)
. . . . . . . . . . . . . .
71
19
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see
TB493
Recommended Operating Conditions
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4.
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief
TB379.
5. For
JC
, the “case temp” location is taken at the package top center.
Analog Characteristics
SYMBOL
Across the recommended operating conditions unless otherwise specified.
TEST CONDITIONS
MIN
(Note
6)
TYP
MAX
(Note
6)
±20
+25°C, each pot at 5V, 2.5k
-3
I
W
= ±3mA, V
CC
= 3V to 5V
V
SS
= 0V
Ref: 1kHz
V
w(n)(actual)
- V
w(n)(expected)
V
w(n + 1)
- [V
w(n) + MI
]
-1
-0.2
30
20
See macro model
V
IN
= V
SS
to V
CC
. Device is in stand-by mode.
10/
0.1
10
V
SS
-
1.6
+1
+0.2
50
15
+3
150
V
CC
UNITS
%
mW
mA
Ω
V
dBV
%
MI (Note
9)
MI (Note
9)
ppm/
°
C
ppm/
°
C
pF
µA
PARAMETER
End-to-end Resistance Tolerance
Power Rating
I
W
R
W
V
TERM
Wiper Current
Wiper Resistance
Voltage On Any V
H
/R
H
or V
L
/R
L
pin
Noise
Resolution (Note
10)
Absolute Linearity (Note
7)
Relative Linearity (Note
8)
Temperature Coefficient Of R
TOTAL
Ratiometric Temp. Coefficient
C
H
/C
L
/C
W
I
AL
Potentiometer Capacitances
R
H
, R
L
, R
W
Leakage Current
D.C. OPERATING CHARACTERISTICS
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IH
V
IL
V
OL
V
CC
Supply Current (Active)
V
CC
Supply Current (Nonvolatile Write)
V
CC
Current (Standby)
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
Output LOW Voltage
I
OL
= 3mA
f
SCL
= 400kHz, SDA = open, other inputs = V
SS
f
SCL
= 400kHz, SDA = open, other inputs = V
SS
SCL = SDA = V
CC
, addr. = V
SS
V
IN
= V
SS
to V
CC
V
OUT
= V
SS
to V
CC
V
CC
x 0.7
-0.5
100
1
3
10
10
V
CC
+ 0.5
V
CC
x 0.1
0.4
µA
mA
µA
µA
µA
V
V
V
ENDURANCE AND DATA RETENTION
Minimum Endurance
100,000
Data
changes per
bit per
register
Years
Data Retention
100
FN8192 Rev.6.00
Sep 3, 2015
Page 5 of 19
