X9418
NOT RECOMMENDED FOR NEW DESIGNS
NO RECOMMENDED REPLACEMENT
contact our Technical Support Center at
1-888-INTERSIL or www.intersil.com/tsc
DATASHEET
FN8194
Rev 2.00
October 12, 2006
Low Noise/Low Power/2-Wire Bus Dual Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Two potentiometers in one package
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per
Potentiometer
• Power supplies
—V
CC
= 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications
• High reliability
—Endurance–100,000 Data Changes per Bit per
Register
—Register Data Retention–100 years
• 8-bytes of nonvolatile memory
• 2.5k, 10k resistor array
• Resolution: 64 taps each potentiometer
• 24-pin plastic DIP, 24-lead TSSOP and 24-lead
SOIC packages
• Pb-Free plus anneal available (RoHS compliant)
DESCRIPTION
The X9418 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
V
CC
V
SS
V+
V-
R0 R1
Wiper
Counter
Register
(WCR)
V
H0
/R
H0
WP
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
R2 R3
V
L0
/R
L0
V
W0
/R
W0
8
Data
R0 R1
Wiper
Counter
Register
(WCR)
Resistor
Array
XDCP1
V
W1
/R
W1
V
H1
/R
H1
R2 R3
V
L1
/R
L1
FN8194 Rev 2.00
October 12, 2006
Page 1 of 20
X9418
Ordering Information
V
CC
LIMITS
(V)
PART MARKING
X9418WV
X9418WV Z
X9418WP G
X9418WS G
X9418WS ZG
X9418WV F
2.7 to 5.5
10
5 ±10%
POTENTIOMET
TEMPERATU
ER
ORGANIZATION RE RANGE
(°C)
(k)
10
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
-40 to +85
-40 to +85
2.5
0 to +70
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
PART NUMBER
X9418WV24*
X9418WV24Z* (Note)
X9418WP24I-2.7
X9418WS24I-2.7
X9418WS24IZ-2.7 (Note)
X9418WV24-2.7*
PACKAGE
24 Ld TSSOP (4.4MM)
PKG. DWG. #
MDP0044
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
24 Ld PDIP
24 Ld SOIC (300MIL)
24 Ld SOIC (300MIL) (Pb-free)
24 Ld TSSOP (4.4MM)
E24.6
M24.3
M24.3
MDP0044
X9418WV24Z-2.7* (Note) X9418WV ZF
X9418WV24I-2.7
X9418WV24IZ-2.7 (Note)
X9418YS24-2.7
X9418YS24Z-2.7 (Note)
X9418YS24I-2.7
X9418YS24IZ-2.7 (Note)
X9418YV24I-2.7*
X9418WV G
X9418WV ZG
X9418YS F
X9418YS ZF
X9418YS G
X9418YS ZG
X9418YV G
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
24 Ld TSSOP (4.4MM)
MDP0044
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
24 Ld SOIC (300MIL)
24 Ld SOIC (300MIL) (Pb-free)
24 Ld SOIC (300MIL)
24 Ld SOIC (300MIL) (Pb-free)
24 Ld TSSOP (4.4MM)
M24.3
M24.3
M24.3
M24.3
MDP0044
X9418YV24IZ-2.7* (Note) X9418YV ZG
*Add "T1" suffix for tape and reel.
24 Ld TSSOP (4.4MM) (Pb-free) MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9418.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs. An open drain output requires the use
of a pull-up resistor. For selecting typical values, refer to
the guidelines for calculating typical values on the bus
pull-up resistors graph.
Device Address (A
0
-
A
3
)
The Address inputs are used to set the least significant 4
bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
Address input in order to initiate communication with the
X9418. A maximum of 16 devices may occupy the 2-
wire serial bus.
Potentiometer Pins
V
H
/R
H
(V
H0
/R
H0
- V
H1
/R
H1
), V
L
/R
L
(V
L0
/R
L0
- V
L1
/R
L1
)
The V
H
/R
H
and V
L
/R
L
inputs are equivalent to the
terminal connections on either end of a mechanical
potentiometer.
V
W
/R
W
(V
W0
/R
W0
- V
W1
/R
W1
)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to the
Data Registers.
Analog Supplies V+, V-
The Analog Supplies V+, V- are the supply voltages for
the XDCP analog section.
FN8194 Rev 2.00
October 12, 2006
Page 2 of 20
X9418
PIN CONFIGURATION
DIP/SOIC
V
CC
R
L0
/V
L0
R
H0
/V
H0
R
W0
/V
W0
A2
WP
SDA
A1
R
L1
/V
L1
R
H1
/V
H1
R
W1
/V
W1
V
SS
1
24
2
23
3
22
4
21
5
20
6
19
X9418
7
18
8
17
9
16
10
5
11
14
12
13
V+
NC
NC
NC
A0
NC
A3
SCL
NC
NC
NC
V-
PRINCIPLES OF OPERATION
The X9418 is a highly integrated microcircuit
incorporating two resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
Serial Interface
The X9418 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the
transfer is a master and the device being controlled is
the slave. The master will always initiate data transfers
and provide the clock for both transmit and receive
operations. Therefore, the X9418 will be considered a
slave device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods (t
LOW
). SDA state changes during SCL
HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9418 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9418 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condition
is met.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide a
positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and
during this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
TSSOP
SDA
A1
R
L1
/V
L1
R
H1
/V
H1
R
W1
/V
W1
V
SS
NC
NC
NC
V-
SCL
A3
1
24
2
23
3
22
4
21
5
20
6
19
X9418
7
18
8
17
9
16
10
15
14
11
13
12
WP
A2
V
W0
/R
W0
V
H0
/R
H0
V
L0
/R
L0
V
CC
NC
NC
NC
V+
A0
NC
PIN NAMES
Symbol
SCL
SDA
A0 - A3
V
H0
/R
H0
- V
H1
/R
H1
,
V
L0
/R
L0
- V
L1
/R
L1
V
W0
/R
W0
-
V
W1
/R
W1
WP
V+,V-
V
CC
V
SS
NC
Description
Serial Clock
Serial Data
Device Address
Potentiometer Pins
(terminal equivalent)
Potentiometer Pins
(wiper equivalent)
Hardware Write Protection
Analog Supplies
System Supply Voltage
System Ground
No Connection
FN8194 Rev 2.00
October 12, 2006
Page 3 of 20
X9418
The X9418 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command
byte. If the command is followed by a data byte the
X9418 will respond with a final acknowledge.
Array Description
The X9418 is comprised of two resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array are
equivalent to the fixed terminals of a mechanical
potentiometer (V
H
/R
H
and V
L
/R
L
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(V
W
/R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by the Wiper Counter Register (WCR). The
six bits of the WCR are decoded to select, and enable,
one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
Data Registers into the WCR. These Data Registers and
the WCR can be read and written by the host system.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (refer to Figure 1 below). For the X9418 this is
fixed as 0101[B].
Figure 1. Slave Address
Device Type
Identifier
Once the stop condition is issued to indicate the end of
the nonvolatile write command the X9418 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9418 is still
busy with the write operation no ACK will be returned. If
the X9418 has completed the write operation an ACK
will be returned, and the master can then proceed with
the next operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter ACK Polling
Issue
START
Issue Slave
Address
Issue STOP
ACK
Returned?
YES
NO
Further
Operation?
YES
Issue
Instruction
NO
Issue STOP
0
1
0
1
A3
A2
A1
A0
Proceed
Proceed
Device Address
Instruction Structure
The next byte sent to the X9418 contains the instruction
and register pointer information. The four most significant
bits are the instruction. The next four bits point to one of
the two pots and when applicable they point to one of
four associated registers. The format is shown Figure 2.
The next four bits of the slave address are the device
address. The physical device address is defined by the
state of the A
0
- A
3
inputs. The X9418 compares the
serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9418 to respond with an acknowledge. The A
0
-
A
3
inputs can be actively driven by CMOS input signals
or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal
nonvolatile write operation, can be used to take
advantage of the typical 5ms EEPROM write cycle time.
FN8194 Rev 2.00
October 12, 2006
Page 4 of 20
X9418
Figure 2. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
0
P0
or it may occur globally, wherein the transfer occurs
between both of the potentiometers and one of their
associated registers.
Four instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9418; either between the host and one of
the Data Registers or directly between the host and the
wiper counter register. These instructions are: Read
Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register
(change current wiper position of the selected pot), read
Data Register (read the contents of the selected
nonvolatile register) and write Data Register (write a new
value to the selected Data Register). The sequence of
operations is shown in Figure 4.
The Increment/Decrement command is different from
the other commands. Once the command is issued and
the X9418 has responded with an acknowledge, the
master can clock the selected wiper up and/or down in
one segment steps; thereby, providing a fine tuning
capability to the host. For each SCL clock pulse (t
HIGH
)
while SDA is HIGH, the selected wiper will move one
resistor segment towards the V
H
/R
H
terminal. Similarly,
for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards
the V
L
/R
L
terminal. A detailed illustration of the
sequence and timing for this operation are shown in
Figures 5 and 6 respectively.
Instructions
Wiper Counter
Register Select
The four high order bits define the instruction. The next
two bits (R1 and R0) select one of the four registers that
is to be acted upon when a register oriented instruction
is issued. The last bits (P0) select which one of the two
potentiometers is to be affected by the instruction. Bit 1
is defined to be 0.
Four of the nine instructions end with the transmission of
the instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the wiper counter register and one of the data
registers. A transfer from a Data Register to a Wiper
Counter Register is essentially a write to a static RAM.
The response of the wiper to this action will be delayed
t
WRL
. A transfer from the wiper counter register (current
wiper position), to a Data Register is a write to
nonvolatile memory and takes a minimum of t
WR
to
complete. The transfer can occur between one of the
two potentiometers and one of its associated registers;
Figure 3. Two-Byte Instruction Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1 R0 0
P0
A
C
K
S
T
O
P
FN8194 Rev 2.00
October 12, 2006
Page 5 of 20
模拟与混合信号
