ESIGNS
NEW D NT
E D F OR
ME
MMEND D REPLACE
ECO
E
te r a t
N OT R
MMEND l
Sheet
ort Cen /tsc
p
Data
Sup
PRELIMINARY
CO
ica
com
NO RE
r Techn www.intersil.
t ou
contac TERSIL or
1-888-IN
®
X9438
Programmable Analog
March 11, 2005
FN8199.0
Dual Digitally Controlled Potentiometer
(XDCP™) with Operational Amplifier
FEATURES
Two CMOS voltage operational amplifiers
Two digitally controlled potentiometers
Can be combined or used separately
Amplifiers:
—Low voltage operation
—V+/V- = ±2.7V to ±5.5V
—Rail-to-rail CMOS performance
—1MHz gain bandwidth product
• Digitally controlled potentiometers
—Dual 64 tap potentiometers
—R
total
= 10kΩ
—2-wire serial interface
—V
CC
= 2.7V to 5.5V
•
•
•
•
DESCRIPTION
The X9438 is a monolithic CMOS IC that incorporates
two operational amplifiers and two nonvolatile digitally
controlled potentiometers. The amplifiers are CMOS
differential input voltage operational amplifiers with
near rail-to-rail outputs. All pins for the two amplifiers
are brought out of the package to allow combining
them with the potentiometers, or using them as com-
plete stand-alone amplifiers.
The digitally controlled potentiometers consist of a
series string of 63 polycrystalline resistors that behave
as standard integrated circuit resistors. The two-wire
serial port, common to both pots, allows the user to
program the connection of the wiper output to any of
the resistor nodes in the series string. The wiper posi-
tion is saved in the on board E2 memory to allow for
nonvolatile restoration of the wiper position.
A wide variety of applications can be implemented
using the potentiometers and the amplifiers. A typical
application is to implement the amplifier as a wiper
buffer in circuits that use the potentiometer as a voltage
reference. The potentiometer can also be combined
with the amplifier yielding a digitally programmable gain
amplifier or programmable current source.
BLOCK DIAGRAM
V
CC
R
W0
R
H0
R
L0
V+
V
NI0
SCL
SDA
A3
A2
A1
A0
WP
Control and
Memory
WCR0
+
–
V
OUT0
V
INV0
V
NI1
+
WCR1
–
V
OUT1
V
INV1
V
SS
R
W1
R
L1
R
H1
V-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
|
Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9438
PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9438.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor.
Device Address (A
0
- A
3
)
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9438. A maximum of 16 devices may share the
same 2-wire serial bus.
Potentiometer Pins
(1)
R
H
(R
H0
- R
H1
), R
L
(R
L0
- R
L1
)
The R
H
and R
L
inputs are equivalent to the terminal con-
nections on either end of a mechanical potentiometer.
R
W
(R
W0
- R
W1
)
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Amplifier and Device Pins
Amplifier Input Voltage V
NI
(0,1) and V
INV
(0,1)
V
NI
and V
INV
are inputs to the noninverting (+) and
inverting (-) inputs of the operational amplifiers.
Amplifier Output Voltage V
OUT
(0,1)
V
OUT
is the voltage output pin of the operational
amplifier.
Hardware Write Protect Input WP
The WP pin, when low, prevents non-volatile writes to
the wiper counter registers.
Note:
(1) Alternate designations for R
H
, R
L
, R
W
are V
H
, V
L
, V
W
Analog Supplies V+, V-
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the operational amplifiers.
System Supply V
CC
and Ground V
SS
.
The system supply V
CC
and its reference V
SS
is used
to bias the interface and control circuits.
PIN CONFIGURATION
SOIC
V
CC
R
L0
R
H0
R
W0
A
2
WP
SDA
A1
R
L1
R
H1
R
W1
V
SS
1
2
3
4
5
24
23
22
21
20
V+
NC
A
0
1
2
3
4
5
TSSOP
24
23
22
21
20
A
3
SCL
V
INV1
V
NI1
V
OUT1
V-
V
SS
R
W1
R
H1
R
L1
A
1
SDA
V
OUT0
V
NI0
V
INV0
V
NI0
V
INV0
6
19
X9438
7
18
8
17
9
16
10
11
12
15
14
13
A0
NC
A
3
SCL
V
INV1
V
NI1
V
OUT1
V-
V
OUT0
V+
V
CC
R
L0
R
H0
R
W0
A
2
WR
6
19
X9438
7
18
8
17
9
16
10
11
12
15
14
13
PIN NAMES
Symbol
SCL
SDA
A0 - A3
R
H0
- R
H1
,
R
L0
- R
L1
R
W0
- R
W1
V
NI(0,1)
,
V
INV(0,1)
V
OUT0,
V
OUT1
WP
V+,V-
V
CC
V
SS
NC
Serial Data
Device Address
Potentiometers (terminal equivalent)
Potentiometers (wiper equivalent)
Amplifier Input Voltages
Amplifier Outputs
Hardware Write Protection
Analog and Voltage Amplifier Supplies
System/Digital Supply Voltage
System Ground
No Connection
Description
Serial Clock
2
FN8199.0
March 11, 2005
X9438
PRINCIPLES OF OPERATION
The X9438 is an integrated microcircuit incorporating
two resistor arrays, two operational amplifiers and
their associated registers and counters; and the serial
interface logic providing direct communication
between the host and the digitally controlled potenti-
ometers and operational amplifiers.
Serial Interface
The X9438 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers and pro-
vide the clock for both transmit and receive operations.
Therefore, the X9438 will be considered a slave
device in all applications.
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW periods (t
LOW
). SDA state changes during
SCL HIGH are reserved for indicating start and stop
conditions.
Start Condition
All commands to the X9438 are preceded by the start
condition, which is a HIGH to LOW transition of SDA
while SCL is HIGH (t
HIGH
). The X9438 continuously
monitors the SDA and SCL lines for the start condition
and will not respond to any command until this condi-
tion is met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA while
SCL is HIGH.
Acknowledge
Acknowledge is a software convention used to provide
a positive handshake between the master and slave
devices on the bus to indicate the successful receipt of
data. The transmitting device, either the master or the
slave, will release the SDA bus after transmitting eight
bits. The master generates a ninth clock cycle and dur-
ing this period the receiver pulls the SDA line LOW to
acknowledge that it successfully received the eight bits
of data.
The X9438 will respond with an acknowledge after
recognition of a start condition and its slave address
and once again after successful receipt of the com-
mand byte. If the command is followed by a data byte
the X9438 will respond with a final acknowledge.
Operational Amplifier
The voltage operational amplifiers are CMOS rail-to-
rail output general purpose amplifiers. They are
designed to operate from dual (±) power supplies. The
amplifiers may be configured like any standard ampli-
fier. All pins are externally available to allow connec-
tions with the potentiometers or as stand alone
amplifiers.
Potentiometer/Array Description
The X9438 is comprised of two resistor arrays and two
operational amplifiers. Each array contains 63 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
terminals of a mechanical potentiometer (RH and RL
inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R
W
) output. Within each individual array only one
switch may be turned on at a time. These switches are
controlled by a volatile wiper counter register (WCR).
The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches.
The WCR may be written directly, or it can be changed
by transferring the contents of one of four associated
data registers into the WCR. These data registers and
the WCR can be read and written by the host system.
INSTRUCTIONS AND PROGRAMMING
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most signifi-
cant four bits of the slave address are the device type
identifier (refer to Figure 1). For the X9438 this is fixed
as 0101[B].
Figure 1. Address/Identification Byte Format
Device Type
Identifier
0
1
0
1
A3
A2
A1
A0
Device Address
3
FN8199.0
March 11, 2005
X9438
The next four bits of the slave address are the device
address. The physical device address is defined by
the state of the A
0
- A
3
inputs. The X9438 compares
the serial data stream with the address input state; a
successful compare of all four address bits is required
for the X9438 to respond with an acknowledge. The
A
0
- A
3
inputs can be actively driven by CMOS input
signals or tied to V
CC
or V
SS
.
Acknowledge Polling
The disabling of the inputs, during the internal non-vol-
atile write operation, can be used to take advantage of
the typical 5ms EEPROM write cycle time. Once the
stop condition is issued to indicate the end of the non-
volatile write command the X9438 initiates the internal
write cycle. ACK polling (Flow 1) can be initiated
immediately. This involves issuing the start condition
followed by the device slave address. If the X9438 is
still busy with the write operation no ACK will be
returned. If the X9438 has completed the write opera-
tion an ACK will be returned and the master can then
proceed with the next operation.
Flow 1. ACK Polling Sequence
Nonvolatile Write
Command Completed
Enter Ack Polling
Issue
START
Issue Slave
Address
ACK
Returned?
Yes
Further
Operation?
Yes
Issue
Instruction
Issue STOP
No
No
Instruction Structure
The byte following the address contains the instruction
and register pointer information. The four most signifi-
cant bits are the instruction. The next four bits point to
one of the two pots and when applicable they point to
one of the four WCRs associated data registers. The
format is shown below in Figure 2.
Figure 2. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
0
P0
Instructions
WCR Select
The four high order bits define the instruction. The
next two bits (R1 and R0) select one of the two regis-
ters that is to be acted upon when a register oriented
instruction is issued. The last bit (P0) selects which
one of the two potentiometers is to be affected by the
instruction.
Four of the nine instructions end with the transmission
of the instruction byte. The basic sequence is illus-
trated in Figure 3. These two-byte instructions
exchange data between the wiper counter register and
one of the data registers. A transfer from a data regis-
ter to a wiper counter register is essentially a write to a
static RAM. The response of the wiper to this action
will be delayed t
WRL
. A transfer from the wiper counter
register (current wiper position) to a data register is a
write to non-volatile memory and takes a minimum of
t
WR
to complete. The transfer can occur between one
of the two potentiometers and one of its associated
registers; or it may occur globally, wherein the transfer
occurs between all of the potentiometers and one of
their associated registers.
Four instructions require a three-byte sequence to
complete. The basic sequence is illustrated in Figure
4. These instructions transfer data between the host
and the X9438; either between the host and one of the
data registers or directly between the host and the
wiper counter and analog control registers. These
instructions are: 1) Read Wiper Counter Register or
read the current wiper position of the selected pot, 2)
Write Wiper Counter Register, i.e. change current
wiper position of the selected pot; 3) Read Data Regis-
ter, read the contents of the selected non-volatile regis-
ter; 4) Write Data Register, write a new value to the
selected data register. The bit structures of the instruc-
tions are shown in Figure 6.
Issue STOP
Prooceed
Prooceed
4
FN8199.0
March 11, 2005
X9438
Figure 3. Two-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3
A2
A1
A0
A
C
K
I3
I2
I1
I0
R1 R0 0
P0
A
C
K
S
T
O
P
Figure 4. Three-Byte Command Sequence
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0 A
C
K
I3
I2
I1 I0
0
P0 R1 R0 A
C
K
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
The Increment/Decrement command is different from
the other commands. Once the command is issued
and the X9438 has responded with an acknowledge,
the master can clock the selected wiper up and/or
down in one segment steps; thereby, providing a fine
tuning capability to the host. For each SCL clock pulse
Figure 5. Increment/Decrement Command Sequence
SCL
(t
HIGH
) while SDA is HIGH, the selected wiper will
move one resistor segment towards the V
H
terminal.
Similarly, for each SCL clock pulse while SDA is LOW,
the selected wiper will move one resistor segment
towards the V
L
terminal. A detailed illustration of the
sequence for this operation is shown in Figure 5.
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1
I0
X
X
I
N
C
1
I
N
C
2
I
N
C
n
D
E
C
1
D
E
C
n
S
T
O
P
P1 P0 R1 R0 A
C
K
5
FN8199.0
March 11, 2005
