89
Spartan-6 FPGA Data Sheet:
DC and Switching Characteristics
DS162 (v2.4) September 14, 2011
Preliminary Product Specification
Spartan-6 FPGA Electrical Characteristics
Spartan®-6 LX and LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and
AC electrical parameters of the Automotive XA Spartan-6 FPGAs and Defense-grade Spartan-6Q FPGAs devices are
equivalent to the commercial specifications except where noted. The timing characteristics of the commercial (XC) -2 speed
grade industrial device are the same as for a -2 speed grade commercial device. The -2Q and -3Q speed grades are
exclusively for the expanded (Q) temperature range. The timing characteristics are equivalent to those shown for the -2 and
-3 speed grades for the Automotive and Defense-grade devices.
Spartan-6 FPGA DC and AC characteristics are specified for commercial (C), industrial (I), and expanded (Q) temperature
ranges. Only selected speed grades and/or devices might be available in the industrial or expanded temperature ranges for
Automotive and Defense-grade devices. References to device names refer to all available variations of that part number (for
example, LX75 could denote XC6SLX75, XA6SLX75, or XQ6SLX75).The Spartan-6 FPGA -3N speed grade designates
devices that do not support MCB functionality.
All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters
included are common to popular designs and typical applications.
Available device and package combinations can be found at:
•
•
•
DS160:
Spartan-6 Family Overview
DS170:
Automotive XA Spartan-6 Family Overview
DS172:
Defense-Grade Spartan-6Q Family Overview
This Spartan-6 FPGA data sheet, part of an overall set of documentation on the Spartan-6 family of FPGAs, is available on
the Xilinx website at
http://www.xilinx.com/support/documentation/spartan-6.htm.
Spartan-6 FPGA DC Characteristics
Table 1:
Absolute Maximum Ratings
(1)
Symbol
V
CCINT
V
CCAUX
V
CCO
V
BATT
V
FS
V
REF
Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
Output drivers supply voltage relative to GND
Key memory battery backup supply (LX75, LX75T, LX100, LX100T, LX150, and LX150T only)
External voltage supply for eFUSE programming (LX75, LX75T, LX100, LX100T, LX150, and
LX150T only)
(2)
Input reference voltage
Description
–0.5 to 1.32
–0.5 to 3.75
–0.5 to 3.75
–0.5 to 4.05
–0.5 to 3.75
–0.5 to 3.75
Units
V
V
V
V
V
V
© 2009–2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Zynq, Artix, Kintex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS162 (v2.4) September 14, 2011
Preliminary Product Specification
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1
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 1:
Absolute Maximum Ratings
(1)
(Cont’d)
Symbol
Description
DC
Commercial
20% overshoot duration
8% overshoot duration
(5)
DC
All user and dedicated
Industrial
I/Os
20% overshoot duration
4% overshoot duration
(5)
DC
Expanded (Q) 20% overshoot duration
V
IN
and V
TS(3)
I/O input voltage or voltage
applied to 3-state output,
relative to GND
(4)
Commercial
4% overshoot duration
(5)
20% overshoot duration
10% overshoot duration
Restricted to
maximum of 100 user
I/Os
20% overshoot duration
Industrial
10% overshoot duration
8% overshoot duration
(5)
20% overshoot duration
Expanded (Q) 10% overshoot duration
8% overshoot duration
(5)
T
STG
Storage temperature (ambient)
Maximum soldering temperature
(6)
(TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256)
T
SOL
Maximum soldering temperature
(6)
(Pb-free packages: FGG484, FGG676, and FGG900)
Maximum soldering temperature
(6)
(Pb packages: CS484, FT256, FG484, FG676, and FG900)
T
j
Notes:
1.
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
When programming eFUSE, V
FS
V
CCAUX
. Requires up to 40 mA current. For read mode, V
FS
can be between GND and 3.45 V.
I/O absolute maximum limit applied to DC and AC signals. Overshoot duration is the percentage of a data period that the I/O is stressed
beyond 3.45V.
For I/O operation, refer to
UG381:
Spartan-6 FPGA SelectIO Resources User Guide.
Maximum percent overshoot duration to meet 4.40V maximum.
For soldering guidelines and thermal considerations, see
UG385:
Spartan-6 FPGA Packaging and Pinout Specification.
Units
–0.60 to 4.10
–0.75 to 4.25
–0.75 to 4.40
–0.60 to 3.95
–0.75 to 4.15
–0.75 to 4.40
–0.60 to 3.95
–0.75 to 4.15
–0.75 to 4.40
–0.75 to 4.35
–0.75 to 4.45
–0.75 to 4.25
–0.75 to 4.35
–0.75 to 4.40
–0.75 to 4.25
–0.75 to 4.35
–0.75 to 4.40
–65 to 150
+260
+250
+220
+125
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
°C
°C
15% overshoot duration
(5)
–0.75 to 4.40
Maximum junction temperature
(6)
2.
3.
4.
5.
6.
DS162 (v2.4) September 14, 2011
Preliminary Product Specification
www.xilinx.com
2
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 2:
Recommended Operating Conditions
(1)
Symbol
Description
-3, -3N, -2
V
CCINT
Internal supply voltage relative to GND
-3, -2
-1L
V
CCAUX(3)(4)
Auxiliary supply voltage relative to GND
V
CCO(6)(7)(8)
Output supply voltage relative to GND
All I/O
standards
(except PCI)
Commercial temperature (C)
Industrial temperature (I)
Expanded (Q) temperature
Standard performance
(2)
Extended performance
(2)
Standard performance
(2)
Min
1.14
1.2
0.95
2.375
3.15
1.1
–0.5
–0.5
–0.5
–0.5
–
–
1.0
0
–40
–40
Typ
1.2
1.23
1.0
2.5
3.3
–
–
–
–
–
–
–
–
–
–
–
Max
1.26
1.26
1.05
2.625
3.45
3.45
4.0
3.95
3.95
V
CCO
+ 0.5
10
7
3.6
85
100
125
Units
V
V
V
V
V
V
V
V
V
V
mA
mA
V
°C
°C
°C
V
CCAUX
= 2.5V
(5)
V
CCAUX
= 3.3V
V
IN
Input voltage relative to GND
PCI I/O standard
(9)
I
IN(10)
V
BATT(11)
Maximum current through pin using PCI I/O standard
when forward biasing the clamp diode.
(9)
Commercial (C) and
Industrial temperature (I)
Expanded (Q) temperature
Battery voltage relative to GND, T
j
= 0C to +85C
(LX75, LX75T, LX100, LX100T, LX150, and LX150T only)
Commercial (C) range
T
j
Junction temperature operating range
Industrial temperature (I) range
Expanded (Q) temperature range
Notes:
1.
2.
All voltages are relative to ground.
See
Interface Performances for Memory Interfaces
in
Table 25.
The extended performance range is specified for designs not using the
standard V
CCINT
voltage range. The standard V
CCINT
voltage range is used for:
•
•
•
•
Designs that do not use an MCB
LX4 devices
Devices in the TQG144 or CPG196 packages
Devices with the -3N speed grade
3.
4.
5.
Recommended maximum voltage droop for V
CCAUX
is 10 mV/ms.
During configuration, if V
CCO_2
is 1.8V, then V
CCAUX
must be 2.5V.
The -1L devices require V
CCAUX
= 2.5V when using the LVDS_25, LVDS_33, BLVDS_25, LVPECL_25, RSDS_25, RSDS_33, PPDS_25,
and PPDS_33 I/O standards on inputs. LVPECL_33 is not supported in the -1L devices.
6. Configuration data is retained even if V
CCO
drops to 0V.
7. Includes V
CCO
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
8. For PCI systems, the transmitter and receiver should have common supplies for V
CCO
.
9. Devices with a -1L speed grade do not support Xilinx PCI IP.
10. Do not exceed a total of 100 mA per bank.
11. V
BATT
is required to maintain the battery backed RAM (BBR) AES key when V
CCAUX
is not applied. Once V
CCAUX
is applied, V
BATT
can be
unconnected. When BBR is not used, Xilinx recommends connecting to V
CCAUX
or GND. However, V
BATT
can be unconnected.
DS162 (v2.4) September 14, 2011
Preliminary Product Specification
www.xilinx.com
3
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 3:
eFUSE Programming Conditions
(1)
Symbol
V
FS(2)
I
FS
V
CCAUX
V
CCINT
t
j
Notes:
1.
2.
3.
These specifications apply during programming of the eFUSE AES key. Programming is only supported through JTAG.The AES key is only
supported in the following devices: LX75, LX75T, LX100, LX100T, LX150, and LX150T.
When programming eFUSE, V
FS
must be less than or equal to V
CCAUX
. When not programming or when eFUSE is not used, Xilinx
recommends connecting V
FS
to GND. However, V
FS
can be between GND and 3.45 V.
An R
FUSE
resistor is required when programming the eFUSE AES key. When not programming or when eFUSE is not used, Xilinx
recommends connecting the R
FUSE
pin to V
CCAUX
or GND. However, R
FUSE
can be unconnected.
Description
External voltage supply
V
FS
supply current
Auxiliary supply voltage relative to GND
Min
3.2
–
3.2
1129
1.14
15
Typ
3.3
–
3.3
1140
1.2
–
Max
3.4
40
3.45
1151
1.26
85
Units
V
mA
V
V
°C
R
FUSE(3)
External resistor from R
FUSE
pin to GND
Internal supply voltage relative to GND
Temperature range
DS162 (v2.4) September 14, 2011
Preliminary Product Specification
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4
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Table 4:
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRAUX
I
REF
Description
Data retention V
CCINT
voltage (below which configuration data might be lost)
Data retention V
CCAUX
voltage (below which configuration data might be lost)
V
REF
leakage current per pin for commercial (C) and industrial (I) devices
V
REF
leakage current per pin for expanded (Q) devices
Input or output leakage current per pin (sample-tested) for commercial (C) and industrial
(I) devices
Input or output leakage current per pin (sample-tested) for expanded (Q) devices
Leakage current on pins during hot
socketing with FPGA unpowered
Die input capacitance at the pad
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 3.3V or V
CCAUX
= 3.3V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 2.5V or V
CCAUX
= 2.5V
All pins except PROGRAM_B, DONE, and
JTAG pins when HSWAPEN = 1
PROGRAM_B, DONE, and JTAG pins, or other
pins when HSWAPEN = 0
Min
0.8
2.0
–10
–15
–10
–15
–20
Typ
–
–
–
–
–
–
–
I
HS
+ I
RPU
Max
–
–
10
15
10
15
20
Units
V
V
µA
µA
µA
µA
µA
µA
I
L
I
HS
C
IN(1)
–
200
120
60
40
12
200
140
–
–
23
20
39
32
56
47
11
21
29
–
–
–
–
–
–
–
–
–
100
25
25
50
50
75
75
25
50
75
10
500
350
200
150
100
550
400
150
–
55
55
72
74
109
115
52
96
145
pF
µA
µA
µA
µA
µA
µA
µA
nA
I
RPU
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.8V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.5V
Pad pull-up (when selected) @ V
IN
= 0V, V
CCO
= 1.2V
Pad pull-down (when selected) @ V
IN
= V
CCO
, V
CCAUX
= 3.3V
Pad pull-down (when selected) @ V
IN
= V
CCO
, V
CCAUX
= 2.5V
Battery supply current
Resistance of optional input differential termination circuit, V
CCAUX
= 3.3V
Thevenin equivalent resistance of programmable input termination to V
CCO
(UNTUNED_SPLIT_25) for commercial (C) and industrial (I) devices
Thevenin equivalent resistance of programmable input termination to V
CCO
(UNTUNED_SPLIT_25) for expanded (Q) devices
Thevenin equivalent resistance of programmable input termination to V
CCO
(UNTUNED_SPLIT_50) for commercial (C) and industrial (I) devices
Thevenin equivalent resistance of programmable input termination to V
CCO
(UNTUNED_SPLIT_50) for expanded (Q) devices
Thevenin equivalent resistance of programmable input termination to V
CCO
(UNTUNED_SPLIT_75) for commercial (C) and industrial (I) devices
Thevenin equivalent resistance of programmable input termination to V
CCO
(UNTUNED_SPLIT_75) for expanded (Q) devices
Thevenin equivalent resistance of programmable output termination (UNTUNED_25)
I
RPD
I
BATT(2)
R
DT(3)
R
IN_TERM(5)
R
OUT_TERM
Thevenin equivalent resistance of programmable output termination (UNTUNED_50)
Thevenin equivalent resistance of programmable output termination (UNTUNED_75)
Notes:
1.
2.
3.
4.
5.
The C
IN
measurement represents the die capacitance at the pad, not including the package.
Maximum value specified for worst case process at 25°C. LX75, LX75T, LX100, LX100T, LX150, and LX150T only.
Refer to IBIS models for R
DT
variation and for values at V
CCAUX
= 2.5V. IBIS values for R
DT
are valid for all temperature ranges.
V
CCO2
is not required for data retention. The minimum V
CCO2
for power-on reset and configuration is 1.65V.
Termination resistance to a V
CCO
/2 level.
DS162 (v2.4) September 14, 2011
Preliminary Product Specification
www.xilinx.com
5
