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DS026 (v3.10) April 17, 2003
Product Specification
www.xilinx.com
1-800-255-7778
1
XC18V00 Series In-System Programmable Configuration PROMs
R
CLK CE
OE/Reset
TCK
TMS
TDI
TDO
Control
and
JTAG
Interface
Data
Memory
Address
Data
Serial
or
Parallel
Interface
7
CEO
D0 DATA
Serial or Parallel Mode
D[1:7]
Parallel Interface
CF
DS026_01_090502
Figure 1:
XC18V00 Series Block Diagram
Pinout and Pin Description
Pins not listed are "no connects."
Table 1:
Pin Names and Descriptions
Pin
Name
D0
Boundary
Scan
Order
4
3
D1
6
5
D2
2
1
D3
8
7
D4
24
23
D5
10
9
D6
17
16
D7
14
13
44-pin
VQFP
40
44-pin
PLCC
2
20-pin
SOIC &
PLCC
1
Function
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
Pin Description
D0 is the DATA output pin to provide data for
configuring an FPGA in serial mode.
D0-D7 are the output pins to provide parallel
data for configuring a Xilinx FPGA in
Slave-Parallel/SelectMap mode.
29
35
16
42
4
2
27
33
15
9
15
7
(1)
25
31
14
14
20
9
19
25
12
2
www.xilinx.com
1-800-255-7778
DS026 (v3.10) April 17, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions
(Continued)
Pin
Name
CLK
Boundary
Scan
Order
0
44-pin
VQFP
43
44-pin
PLCC
5
20-pin
SOIC &
PLCC
3
Function
DATA IN
Pin Description
Each rising edge on the CLK input increments
the internal address counter if both CE is Low
and OE/RESET is High.
When Low, this input holds the address
counter reset and the DATA output is in a
high-impedance state. This is a bidirectional
open-drain pin that is held Low while the
PROM is reset. Polarity is NOT
programmable.
When CE is High, the device is put into
low-power standby mode, the address
counter is reset, and the DATA pins are put in
a high-impedance state.
Allows JTAG CONFIG instruction to initiate
FPGA configuration without powering down
FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
Chip Enable Output (CEO) is connected to
the CE input of the next PROM in the chain.
This output is Low when CE is Low and
OE/RESET input is High, AND the internal
address counter has been incremented
beyond its Terminal Count (TC) value. CEO
returns to High when OE/RESET goes Low or
CE goes High.
GND is the ground connection.
OE/
RESET
20
19
18
DATA IN
DATA OUT
OUTPUT
ENABLE
DATA IN
13
19
8
CE
15
15
21
10
CF
22
21
DATA OUT
OUTPUT
ENABLE
DATA OUT
OUTPUT
ENABLE
10
16
7
(1)
CEO
12
11
21
27
13
GND
TMS
MODE
SELECT
6, 18, 28 &
41
5
3, 12, 24
& 34
11
11
5
The state of TMS on the rising edge of TCK
determines the state transitions at the Test
Access Port (TAP) controller. TMS has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the device if the pin is not
driven.
This pin is the JTAG test clock. It sequences
the TAP controller and all the JTAG test and
programming electronics.
This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the system if the pin is
not driven.
This pin is the serial output for all JTAG
instruction and data registers. TDO has an
internal 50K ohm resistive pull-up on it to
provide a logic “1” to the system if the pin is
not driven.
Positive 3.3V supply voltage for internal logic
and input buffers.
TCK
CLOCK
7
13
6
TDI
DATA IN
3
9
4
TDO
DATA OUT
31
37
17
V
CC
17, 35 &
38
23, 41 &
44
18 & 20
DS026 (v3.10) April 17, 2003
Product Specification
www.xilinx.com
1-800-255-7778
3
XC18V00 Series In-System Programmable Configuration PROMs
Table 1:
Pin Names and Descriptions
(Continued)
Pin
Name
V
CCO
NC
Boundary
Scan
Order
44-pin
VQFP
8, 16, 26 &
36
1, 2, 4,
11, 12, 20,
22, 23, 24,
30, 32, 33,
34, 37, 39,
44
44-pin
PLCC
14, 22,
32 & 42
1, 6, 7, 8,
10, 17,
18, 26,
28, 29,
30, 36,
38, 39,
40, 43
20-pin
SOIC &
PLCC
19
R
Function
Pin Description
Positive 3.3V or 2.5V supply voltage
connected to the output voltage drivers.
No connects.
Notes:
1. By default, pin 7 is the D4 pin in the 20-pin packages. However, CF --> D4 programming option can be set to override the default and
route the CF function to pin 7 in the Serial mode.
Pinout Diagrams
NC
CLK
D2
GND
D0
NC
VCC
NC
V
CCO
VCC
NC
NC
CLK
D2
GND
D0
NC
VCC
NC
V
CCO
VCC
NC
39
38
37
36
35
34
33
32
31
30
29
NC
NC
TDO
NC
D1
GND
D3
V
CCO
D5
NC
NC
NC
NC
TDI
NC
TMS
GND
TCK
V
CCO
D4
CF
NC
1
2
3
4
5
6
7
8
9
10
11
44
43
42
41
40
39
38
37
36
35
34
NC
NC
TDI
NC
TMS
GND
TCK
V
CCO
D4
CF
NC
7
8
9
10
11
12
13
14
15
16
17
6
5
4
3
2
1
44
43
42
41
40
PC44
Top View
VQ44
Top View
33
32
31
30
29
28
27
26
25
24
23
NC
NC
TDO
NC
D1
GND
D3
V
CCO
D5
NC
NC
18
19
20
21
22
23
24
25
26
27
28
NC
OE/RESET
D6
CE
V
CCO
VCC
GND
D7
NC
CEO
NC
DS026_12_090602
NC
OE/RESET
D6
CE
V
CCO
VCC
GND
D7
NC
CEO
NC
12
13
14
15
16
17
18
19
20
21
22
DS026_13_090602
4
www.xilinx.com
1-800-255-7778
DS026 (v3.10) April 17, 2003
Product Specification
R
XC18V00 Series In-System Programmable Configuration PROMs
工控电子
