0
R
Spartan-3E FPGA Family:
Complete Data Sheet
0
0
DS312 November 9, 2006
Product Specification
Module 1:
Introduction and Ordering Information
DS312-1 (v3.4) November 9, 2006
•
•
•
•
•
Introduction
Features
Architectural Overview
Package Marking
Ordering Information
Module 3:
DC and Switching Characteristics
DS312-3 (v3.4) November 9, 2006
•
DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
Switching Characteristics
- I/O Timing
- SLICE Timing
- DCM Timing
- Block RAM Timing
- Multiplier Timing
- Configuration and JTAG Timing
•
Module 2:
Functional Description
DS312-2 (v3.4) November 9, 2006
•
Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
Configurable Logic Block (CLB)
Block RAM
Dedicated Multipliers
Digital Clock Manager (DCM)
Clock Network
Configuration
Powering Spartan-3E FPGAs
Production Stepping
•
•
•
•
•
•
•
•
Module 4:
Pinout Descriptions
DS312-4 (v3.4) November 9, 2006
•
•
•
•
Pin Descriptions
Package Overview
Pinout Tables
Footprint Diagrams
© 2005-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 November 9, 2006
www.xilinx.com
1
Complete Data Sheet
R
2
www.xilinx.com
DS312 November 9, 2006
Product Specification
8
R
Spartan-3E FPGA Family:
Introduction and Ordering
Information
0
DS312-1 (v3.4) November 9, 2006
Product Specification
Introduction
The Spartan™-3E family of Field-Programmable Gate
Arrays (FPGAs) is specifically designed to meet the needs
of high volume, cost-sensitive consumer electronic applica-
tions. The five-member family offers densities ranging from
100,000 to 1.6 million system gates, as shown in
Table 1.
The Spartan-3E family builds on the success of the earlier
Spartan-3 family by increasing the amount of logic per I/O,
significantly reducing the cost per logic cell. New features
improve system performance and reduce the cost of config-
uration. These Spartan-3E enhancements, combined with
advanced 90 nm process technology, deliver more function-
ality and bandwidth per dollar than was previously possible,
setting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3E FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection, and digital television equipment.
The Spartan-3E family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
True LVDS, RSDS, mini-LVDS, differential
HSTL/SSTL differential I/O
- Enhanced Double Data Rate (DDR) support
- DDR SDRAM support up to 333 Mb/s
Abundant, flexible logic resources
- Densities up to 33,192 logic cells, including
optional shift register or distributed RAM support
- Efficient wide multiplexers, wide logic
- Fast look-ahead carry logic
- Enhanced 18 x 18 multipliers with optional pipeline
- IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
- Up to 648 Kbits of fast block RAM
- Up to 231 Kbits of efficient distributed RAM
Up to eight Digital Clock Managers (DCMs)
- Clock skew elimination (delay locked loop)
- Frequency synthesis, multiplication, division
- High-resolution phase shifting
- Wide frequency range (5 MHz to over 300 MHz)
Eight global clocks plus eight additional clocks per
each half of device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
- Low-cost, space-saving SPI serial Flash PROM
- x8 or x8/x16 parallel NOR Flash PROM
- Low-cost Xilinx
Platform Flash
with JTAG
Complete Xilinx
ISE™
and
WebPACK™
development
system support
MicroBlaze™
and
PicoBlaze™
embedded processor
cores
Fully compliant 32-/64-bit 33 MHz PCI support
(66 MHz in some devices)
Low-cost QFP and BGA packaging options
- Common footprints support easy density migration
- Pb-free packaging options
-
•
•
•
•
•
Features
Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
• Proven advanced 90-nanometer process technology
• Multi-voltage, multi-standard SelectIO™ interface pins
- Up to 376 I/O pins or 156 differential signal pairs
- LVCMOS, LVTTL, HSTL, and SSTL single-ended
signal standards
- 3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
- 622+ Mb/s data transfer rate per I/O
Table 1:
Summary of Spartan-3E FPGA Attributes
Equivalent
Logic
Rows Columns
Cells
2,160
5,508
10,476
19,512
22
34
46
60
16
26
34
46
CLB Array
(One CLB = Four Slices)
Total
CLBs
240
612
1,164
2,168
3,688
Total
Slices
960
2,448
4,656
8,672
14,752
•
•
•
•
•
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
System
Gates
100K
250K
500K
1200K
Distributed
RAM bits
(1)
15K
38K
73K
136K
231K
Block
RAM
bits
(1)
72K
216K
360K
504K
648K
Dedicated
Multipliers DCMs
4
12
20
28
36
2
4
4
8
8
Maximum
Maximum Differential
I/O Pairs
User I/O
108
172
232
304
376
40
68
92
124
156
XC3S1600E 1600K
33,192
76
58
Notes:
1.
By convention, one Kb is equivalent to 1,024 bits.
© 2005-2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-1 (v3.4) November 9, 2006
Product Specification
www.xilinx.com
3
Introduction and Ordering Information
R
Architectural Overview
The Spartan-3E family architecture consists of five funda-
mental programmable functional elements:
•
Configurable Logic Blocks (CLBs)
contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs)
control the flow of data
between the I/O pins and the internal logic of the
device. Each IOB supports bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including four high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM
provides data storage in the form of
18-Kbit dual-port blocks.
Multiplier Blocks
accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks
provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
These elements are organized as shown in
Figure 1.
A ring
of IOBs surrounds a regular array of CLBs. Each device has
two columns of block RAM except for the XC3S100E, which
has one column. Each RAM column consists of several
18-Kbit RAM blocks. Each block RAM is associated with a
dedicated multiplier. The DCMs are positioned in the center
with two at the top and two at the bottom of the device. The
XC3S100E has only one DCM at the top and bottom, while
the XC3S1200E and XC3S1600E add two DCMs in the
middle of the left and right sides.
The Spartan-3E family features a rich network of traces that
interconnect all five functional elements, transmitting sig-
nals among them. Each functional element has an associ-
ated switch matrix that permits multiple connections to the
routing.
•
•
Notes:
1.
The XC3S1200E and XC3S1600E have two additional DCMs on both the left and right sides as
indicated by the dashed lines. The XC3S100E has only one DCM at the top and one at the bottom.
Figure 1:
Spartan-3E Family Architecture
4
www.xilinx.com
DS312-1 (v3.4) November 9, 2006
Product Specification
R
Introduction and Ordering Information
Configuration
Spartan-3E FPGAs are programmed by loading configura-
tion data into robust, reprogrammable, static CMOS config-
uration latches (CCLs) that collectively control all functional
elements and routing resources. The FPGA’s configuration
data is stored externally in a PROM or some other non-vol-
atile medium, either on or off the board. After applying
power, the configuration data is written to the FPGA using
any of seven different modes:
•
•
•
•
•
•
Master Serial from a Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up or Down from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester.
I/O Capabilities
The Spartan-3E FPGA SelectIO interface supports many
popular single-ended and differential standards.
Table 2
shows the number of user I/Os as well as the number of dif-
ferential I/O pairs available for each device/package combi-
nation.
Spartan-3E FPGAs support the following single-ended
standards:
•
•
•
•
•
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3V PCI at 33 MHz, and in some devices,
66 MHz
HSTL I and III at 1.8V, commonly used in memory
applications
SSTL I at 1.8V and 2.5V, commonly used for memory
applications
Spartan-3E FPGAs support the following differential stan-
dards:
•
•
•
•
•
•
•
LVDS
Bus LVDS
mini-LVDS
RSDS
Differential HSTL (1.8V, Types I and III)
Differential SSTL (2.5V and 1.8V, Type I)
2.5V LVPECL inputs
Table 2:
Available User I/Os and Differential (Diff) I/O Pairs
VQ100
VQG100
Device
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Notes:
1.
2.
All Spartan-3E devices provided in the same package are pin-compatible as further described in Module 4:
Pinout Descriptions.
The number shown in
bold
indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins.
CP132
CPG132
User
83
(11)
92
(7)
92
(7)
-
-
Diff
35
(2)
41
(2)
41
(2)
-
-
TQ144
TQG144
User
108
(28)
108
(28)
-
-
-
Diff
40
(4)
40
(4)
-
-
-
PQ208
PQG208
User
-
158
(32)
158
(32)
-
-
Diff
-
65
(5)
65
(5)
-
-
FT256
FTG256
User
-
172
(40)
190
(41)
190
(40)
-
Diff
-
68
(8)
77
(8)
77
(8)
-
FG320
FGG320
User
-
-
232
(56)
250
(56)
250
(56)
Diff
-
-
92
(12)
99
(12)
99
(12)
FG400
FGG400
User
-
-
-
304
(72)
304
(72)
Diff
-
-
-
124
(20)
124
(20)
FG484
FGG484
User
-
-
-
-
376
(82)
Diff
-
-
-
-
156
(21)
User
66
(7)
66
(7)
-
-
-
Diff
30
(2)
30
(2)
-
-
-
DS312-1 (v3.4) November 9, 2006
Product Specification
www.xilinx.com
5
电源技术
