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DS529-1 (v2.0) August 19, 2010
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3
Introduction and Ordering Information
Architectural Overview
The Spartan-3A family architecture consists of five
fundamental programmable functional elements:
•
Configurable Logic Blocks (CLBs)
contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs)
control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus 3-state
operation. Supports a variety of signal standards,
including several high-performance differential
standards. Double Data-Rate (DDR) registers are
included.
Block RAM
provides data storage in the form of 18-Kbit
dual-port blocks.
Multiplier Blocks
accept two 18-bit binary numbers as
inputs and calculate the product.
•
Digital Clock Manager (DCM) Blocks
provide
self-calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
•
•
•
These elements are organized as shown in
Figure 1.
A dual
ring of staggered IOBs surrounds a regular array of CLBs.
Each device has two columns of block RAM except for the
XC3S50A, which has one column. Each RAM column
consists of several 18-Kbit RAM blocks. Each block RAM is
associated with a dedicated multiplier. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device. The XC3S50A has DCMs only at the
top, while the XC3S700A and XC3S1400A add two DCMs in
the middle of the two columns of block RAM and multipliers.
The Spartan-3A family features a rich network of routing that
interconnect all five functional elements, transmitting signals
among them. Each functional element has an associated
switch matrix that permits multiple connections to the
routing.
IOBs
CLB
Block RAM
DCM
IOBs
OBs
DCM
CLBs
Block RAM / Multiplier
IOBs
DCM
IOBs
Notes:
1.
IOBs
Multiplier
DS312-1_01_032606
The XC3S700A and XC3S1400A have two additional DCMs on both the left and right sides as indicated by the
dashed lines. The XC3S50A has only two DCMs at the top and only one Block RAM/Multiplier column.
Figure 1:
Spartan-3A FPGA Architecture
4
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DS529-1 (v2.0) August 19, 2010
Introduction and Ordering Information
Configuration
Spartan-3A FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board. After
applying power, the configuration data is written to the
FPGA using any of seven different modes:
•
•
•
•
•
•
Master Serial from a
Xilinx Platform Flash PROM
Serial Peripheral Interface (SPI) from an
industry-standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an
industry-standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
Boundary Scan (JTAG), typically downloaded from a
processor or system tester
I/O Capabilities
The Spartan-3A FPGA SelectIO interface supports many
popular single-ended and differential standards.
Table 2
shows the number of user I/Os as well as the number of
differential I/O pairs available for each device/package
combination. Some of the user I/Os are unidirectional
input-only pins as indicated in
Table 2.
Spartan-3A FPGAs support the following single-ended
standards:
•
•
•
•
•
3.3V low-voltage TTL (LVTTL)
Low-voltage CMOS (LVCMOS) at 3.3V, 2.5V, 1.8V,
1.5V, or 1.2V
3.3V PCI at 33 MHz or 66 MHz
HSTL I, II, and III at 1.5V and 1.8V, commonly used in
memory applications
SSTL I and II at 1.8V, 2.5V, and 3.3V, commonly used
for memory applications
Furthermore, Spartan-3A FPGAs support MultiBoot
configuration, allowing two or more FPGA configuration
bitstreams to be stored in a single SPI serial Flash or a BPI
parallel NOR Flash. The FPGA application controls which
configuration to load next and when to load it.
Additionally, each Spartan-3A FPGA contains a unique,
factory-programmed Device DNA identifier useful for
tracking purposes, anti-cloning designs, or IP protection.
Table 2:
Available User I/Os and Differential (Diff) I/O Pairs
Package
Body Size
(mm)
Spartan-3A FPGAs support the following differential
standards:
•
•
•
•
•
LVDS, mini-LVDS, RSDS, and PPDS I/O at 2.5V or
3.3V
Bus LVDS I/O at 2.5V
TMDS I/O at 3.3V
Differential HSTL and SSTL I/O
LVPECL inputs at 2.5V or 3.3V
VQ100
VQG100
14 x 14
(2)
TQ144
TQG144
20 x 20
(2)
FT256
FTG256
17 x 17
FG320
FGG320
19 x 19
FG400
FGG400
21 x 21
FG484
FGG484
23 x 23
FG676
FGG676
27 x 27
Device
XC3S50A
XC3S200A
XC3S400A
XC3S700A
XC3S1400A
Notes:
1.
2.
User
68
(13)
68
(13)
-
-
-
Diff
60
(24)
60
(24)
-
-
-
User
108
(7)
-
-
-
-
Diff
50
(24)
-
-
-
-
User
144
(32)
195
(35)
195
(35)
161
(13)
161
(13)
Diff
64
(32)
90
(50)
90
(50)
74
(36)
74
(36)
User
-
248
(56)
251
(59)
-
-
Diff
-
112
(64)
112
(64)
-
-
User
-
-
311
(63)
311
(63)
-
Diff
-
-
142
(78)
142
(78)
-
User
-
-
-
372
(84)
375
(87)
Diff
-
-
-
165
(93)
165
(93)
User
-
-
-
-
502
(94)
Diff
-
-
-
-
227
(131)
The number shown in
bold
indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number
of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins
within I/O banks that are restricted to differential inputs.
The footprints for the VQ/TQ packages are larger than the package body. See the
