0
®
XC4000E High-Reliability
Field Programmable Gate Arrays
0
8*
November 21, 1997 (Version 1.3)
Product Specification
- Program verification
- Internal node observability
• Backward Compatible with XC4000 Devices
• Development System runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
• Available in class Q fully compliant QML and Military
temperature range only
- Certified to MIL-PRF-38535, appendix A QML
(Qualified Manufacturers Listing)
XC4000E High-Reliability Features
• System featured Field-Programmable Gate Arrays
- Select-RAM
TM
memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- 8 global low-skew clock or signal distribution
networks
• System Performance beyond 60 MHz
• Flexible Array Architecture
• Low Power Segmented Routing Architecture
• Systems-Oriented Features
- IEEE 1149.1-compatible boundary scan logic
support
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output
• Configured by Loading Binary File
- Unlimited reprogrammability
• Readback Capability
Table 1: XC4000E Field Programmable Gate Arrays
Max.
Typical
Logic
Max. RAM Gate Range
Gates
Bits
(Logic and
(No RAM) (No Logic)
RAM)*
5,000
6,272
3,000 - 9,000
10,000
13,000
25,000
12,800
18,432
32,768
Xilinx High-Reliability
XC4000E family is supplied under the following standard
microcircuit drawings (SMDs):
XC4005E 5962-97522
XC4010E 5962-97523
XC4013E 5962-97524
XC4025E 5962-97525
For more information contact DSCC (Defense Supply Cen-
ter Columbus) Columbus, Ohio.
Device
XC4005E
XC4010E
XC4013E
XC4025E
CLB
Matrix
14 x 14
Total
CLBs
196
400
576
1,024
Number
of
Flip-Flops
616
1,120
1,536
2,560
Max.
Decode
Inputs
per side
42
60
72
96
Max.
User I/O
112
160
192
256
7,000 - 20,000 20 x 20
10,000 -
30,000
15,000 -
45,000
24 x 24
32 x 32
Packages
PG156,
CB164
PG191,
CB196
PG223,
CB228
PG299,
CB228
* Max values of Typical Gate Range include 20-30% of CLBs used as RAM.
November 21, 1997 (Version 1.3)
8-11
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Switching Characteristics
XC4000E Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
TS
T
STG
T
SOL
T
J
Note 1:
Description
Supply voltage relative to GND
Input voltage relative to GND (Note 1)
Voltage applied to 3-state output (Note 1)
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Junction temperature
Ceramic packages
Value
-0.5 to +7.0
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
-65 to +150
+260
+150
Units
V
V
V
°C
°C
°C
Note 2:
Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.
XC4000E Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
T
IN
Note:
Description
Supply voltage relative to GND, T
C
= -55°C to +125°C
High-level input voltage
Low-level input voltage
Input signal transition time
TTL inputs
TTL inputs
Min
4.5
2.0
0
Max
5.5
V
CC
0.8
250
Units
V
V
V
ns
At case temperatures above those listed as Recommended Operating Conditions, all delay parameters increase by 0.35%
per
°
C.
Input and output Measurement thresholds are: 1.5V for TTL and 2.5V for CMOS.
All specifications are subject to change without notice.
8-12
November 21, 1997 (Version 1.3)
XC4000E DC Characteristics Over Operating Conditions
Symbol
V
OH
V
OL
I
CCO
I
L
C
IN
I
RIN*
I
RLL*
Note 1:
Note 2:
*
Description
High-level output voltage @ I
OH
= -4.0mA, V
CC
min
TTL outputs
Low-level output voltage @ I
OL
= 12.0mA, V
CC
min (Note 1) TTL outputs
Quiescent FPGA supply current (Note 2)
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low
Min
2.4
Max
0.4
50
+10
16
-0.25
2.5
-10
-0.02
0.2
Units
V
V
mA
µA
pF
mA
mA
With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with the development system Tie option.
Characterized Only.
XC4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature)
Speed Grade
Device
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
-4
Max
7.0
11.0
11.5
12.5
7.5
11.5
12.0
13.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
Description
From pad through
Primary buffer,
to any clock K
From pad through
Secondary buffer,
to any clock K
Symbol
T
PG
T
SG
November 21, 1997 (Version 1.3)
8-13
XC4000E High-Reliability Field Programmable Gate Arrays
XC4000E Horizontal Longline Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Speed Grade
Symbol
Device
T
IO1
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
Description
TBUF driving a Horizontal Longline (LL):
-4
Max
5.0
8.0
9.0
11.0
6.0
10.5
11.0
12.0
7.0
8.5
8.7
11.0
1.8
3.0
3.5
4.0
23.0
29.0
32.0
42.0
10.0
13.5
15.0
18.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
I going High or Low to LL going High or Low, while T is Low.
Buffer is constantly active. (Note1)
I going Low to LL going from resistive pull-up High to active Low.
TBUF configured as open-drain. (Note1)
T going Low to LL going from resistive pull-up or floating High to active Low.
TBUF configured as open-drain or active buffer with I = Low.
(Note1)
T going High to TBUF going inactive, not driving LL
T
IO2
T
ON
T
OFF
T going High to LL going from Low to High, pulled up by a single resistor.
(Note 1)
T going High to LL going from Low to High, pulled up by two resistors.
(Note1)
T
PUS
T
PUF
Note 1:
These values include a minimum load. Use the static timing analyzer to determine the delay for each destination.
8-14
November 21, 1997 (Version 1.3)
XC4000E Wide Decoder Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). Values apply to all XC4000E devices unless
otherwise noted.
The following guidelines reflect worst-case values over the recommended operating conditions.
Speed Grade
Device
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
XC4005E
XC4010E
XC4013E
XC4025E
-4
Max
9.5
15.0
16.0
18.0
12.5
18.0
19.0
21.0
10.5
16.0
17.0
19.0
12.5
18.0
19.0
21.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Full length, both pull-ups,
inputs from IOB I-pins
Symbol
T
WAF
Full length, both pull-ups,
inputs from internal logic
T
WAFL
Half length, one pull-up,
inputs from IOB I-pins
T
WAO
Half length, one pull-up,
inputs from internal logic
T
WAOL
Notes: These delays are specified from the decoder input to the decoder output.
Fewer than the specified number of pullup resistors can be used, if desired. Using fewer pullups reduces power consumption
but increases delays. Use the static timing analyzer to determine delays if fewer pullups are used.
November 21, 1997 (Version 1.3)
8-15
