XC61G
Series
Low Voltage Detectors (V
DF
= 0.8V½1.5V)
Standard Voltage Detectors (V
DF
1.6V½6.0V)
ETR0203_005a
■GENERAL
DESCRIPTION
The XC61G series are highly precise, low power consumption voltage detectors, manufactured using CMOS and laser
trimming technologies.
Detect voltage is extremely accurate with minimal temperature drift.
Both CMOS and N-ch open drain output configurations are available.
■APPLICATIONS
●Microprocessor
reset circuitry
●Memory
battery back-up circuits
●Power-on
reset circuits
●Power
failure detection
●System
battery life and charge voltage monitors
■FEATURES
Highly Accurate
:
±2%
Low Power Consumption
: 0.7
μA
[ V
IN
=1.5V ] (TYP.)
Detect Voltage Range
: 0.8V ~ 1.5V in 0.1V
increments (Low Voltage)
: 1.6V½6.0V in 0.1V
increments (Standard Voltage)
Operating Voltage Range
: 0.7V ~ 6.0V (Low Voltage)
: 0.7V½10.0V (Standard Voltage)
Detect Voltage Temperature characteristics
:
±100ppm/℃
(TYP.)
Output Configuration
: N-ch open drain output or CMOS
Operating Ambient Temperature
: -40℃~+85℃
Package
USP-3
Environmentally Friendly:
EU RoHS Compliant, Pb Free
■TYPICAL
APPLICATION CIRCUITS
■TYPICAL
PERFORMANCE CHARACTERISTICS
1/16
XC61G
Series
■PIN
CONFIGURATION
V
IN
V
IN
V
OUT
V
SS
(BOTTOM VIEW)
■PIN
ASSIGNMENT
PIN NUMBER
USP-3
3
1
2
PIN NAME
V
IN
V
SS
V
OUT
FUNCTION
Supply Voltage
Ground
Output
■PRODUCT
CLASSIFICATION
●Ordering
Information
XC61G
①②③④⑤⑥⑦-⑧
(
*1
)
DESIGNATOR
①
ITEM
Output Configuration
SYMBOL
C
N
08 ~ 60
0
2
HR
HR-G
DESCRIPTION
CMOS output
N-ch open drain output
e.g. 0.8V
→ ②0, ③8
e.g. 1.5V
→ ②1, ③5
No delay
Within
±
2%
USP-3
(3,000/Reel)
USP-3
(3,000/Reel)
②③
④
⑤
⑥⑦-⑧
Detect Voltage
Output Delay
Detect Accuracy
Packages
(Order Unit)
(*1)
The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
■BLOCK
DIAGRAMS
(1) CMOS Output
(2) N-ch Open Drain Output
2/16
XC61G
Series
■ABSOLUTE
MAXIMUM RATINGS
Ta = 25℃
PARAMETER
Input Voltage
Output Current
*1
*2
*1
*2
SYMBOL
V
IN
I
OUT
RATINGS
V
SS
-0.3 ~ 9.0
V
SS
-0.3 ~ 12.0
50
50
V
SS
-0.3 ~ V
IN
+0.3
V
SS
-0.3 ~ 9.0
V
SS
-0.3 ~ 12.0
120
-40½+85
-40½+125
UNITS
V
mA
CMOS
Output Voltage
N-ch Open Drain Output *1
N-ch Open Drain Output *2
Power Dissipation
USP-3
Operating Ambient Temperature
Storage Temperature Range
V
OUT
Pd
Topr
Tstg
V
mW
℃
℃
■ELECTRICAL
CHARACTERISTICS
V
DF(T)
= 0.8 to 6.0V ± 2%
PARAMETER
Detect Voltage
Hysteresis Range
SYMBOL
V
DF
V
HYS
V
IN
= 1.5V
V
IN
= 2.0V
V
IN
= 3.0V
V
IN
= 4.0V
V
IN
= 5.0V
V
DF(T)
= 0.8V to 1.5V
V
DF(T)
= 1.6V to 6.0V
N-ch, V
DS
= 0.5V
V
IN
=0.7V
V
IN
=1.0V
V
IN
=1.0V
I
OUT
Output Current
(Standard Voltage)
N-ch, V
DS
= 0.5V
V
IN
=2.0V
V
IN
=3.0V
V
IN
=4.0V
V
IN
=5.0V
CMOS,
P-ch, V
DS
=2.1V
CMOS
Output
Leakage
I
LEAK
(Pch)
Current
N-ch Open
Drain
Temperature
ΔV
DF
/
Characteristics
(ΔTopr½V
DF
)
Delay Time
t
DLY
(V
DR
→
V
OUT
inversion)
NOTE:
＊
1：Low Voltage (V
DF(T)
=0.8Ｖ½1.5V)
2：Standard Voltage (V
DF(T)
=1.6Ｖ½6.0V)
V
DF(T)
: Nominal detect voltage
Release Voltage: V
DR
= V
DF
+ V
HYS
＊
Ta=25℃
CONDITIONS
V
DF(T)
=0.8V~1.5V
*1
V
DF(T)
=1.6V~6.0V
*2
MIN.
V
DF
x 0.98
V
DF
x 0.02
-
-
-
-
-
0.7
0.7
0.10
0.85
-
1.0
3.0
5. 0
6.0
7.0
-
-
-
-
-
TYP.
V
DF
V
DF
x 0.05
0.7
0.8
0.9
1.0
1.1
-
-
0.80
2.70
-7.5
2.2
7.7
10.1
11.5
13.0
-10.0
-10
10
±100
0.03
MAX.
V
DF
x 1.02
V
DF
x 0.08
2.3
2.7
3.0
3.2
3.6
6.0
10.0
-
-
-1.5
-
-
-
-
-
-2.0
-
nA
V
IN
=6.0V, V
OUT
=6.0V
V
IN
=10.0V, V
OUT
=10.0V
*2
-40℃
≦
Topr
≦
85℃
V
DR
→V
OUT
inversion
*1
UNITS
V
V
CIRCUITS
1
1
Supply Current
I
SS
μA
2
Operating Voltage
Output Current
(Low Voltage)
V
IN
V
1
3
4
CMOS, P-ch, V
DS
=2.1V V
IN
=6.0V
mA
3
V
IN
=8.0V
4
V
IN
=V
DF
x0.9, V
OUT
=0V
3
100
-
0.2
ppm/
℃
ms
1
5
3/16
XC61G
Series
■OPERATIONAL
EXPLANATION
●CMOS
output
①
When input voltage (V
IN
) is higher than detect voltage (V
DF
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
②
When input voltage (V
IN
) falls below detect voltage (V
DF
), output voltage (V
OUT
) will be equal to the ground voltage
(V
SS
) level.
③
When input voltage (V
IN
) falls to a level below that of the minimum operating voltage (V
MIN
), output will become
unstable. (As for the N-ch open drain product of XC61CN, the pull-up voltage goes out at the output voltage.)
④
When input voltage (V
IN
) rises above the ground voltage (V
SS
) level, output will be unstable at levels below the
minimum operating voltage (V
MIN
). Between the V
MIN
and detect release voltage (V
DR
) levels, the ground voltage (V
SS
)
level will be maintained.
⑤
When input voltage (V
IN
) rises above detect release voltage (V
DR
), output voltage (V
OUT
) will be equal to V
IN
.
(A condition of high impedance exists with N-ch open drain output configurations.)
⑥
The difference between V
DR
and V
DF
represents the hysteresis range.
●Timing
Chart
4/16
XC61G
Series
■NOTES
ON USE
1. Please use this IC within the stated absolute maximum ratings. For temporary, transitional voltage drop or voltage rising
phenomenon, the IC is liable to malfunction should the ratings be exceeded.
2. When a resistor is connected between the V
IN
pin and the power supply with CMOS output configurations, oscillation may
occur as a result of voltage drops at R
IN
if load current (I
OUT
) exists. (refer to the Oscillation Description (1) below)
3. When a resistor is connected between the V
IN
pin and the power supply with CMOS output configurations, irrespective of
N-ch open-drain output configurations, oscillation may occur as a result of through current at the time of voltage release even
If load current (I
OUT
) does not exist. (refer to the Oscillation Description (2) below )
4. Please use N-ch open drain output configuration, when a resistor R
IN
is connected between the V
IN
pin and power source.
In such cases, please ensure that R
IN
is less than 10kΩ and that C is more than 0.1μF, please test with the actual device.
(refer to the Oscillation Description (1) below)
5. With a resistor R
IN
connected between the V
IN
pin and the power supply, the V
IN
pin voltage will be getting lower than the
power supply voltage as a result of the IC's supply current flowing through the V
IN
pin.
6. In order to stabilize the IC's operations, please ensure that V
IN
pin input frequency's rise and fall times are more than 2
μ
s/ V.
7. Torex places an importance on improving our products and its reliability.
However, by any possibility, we would request user fail-safe design and post-aging treatment on system or equipment.
Power supply
●Oscillation
Description
(1) Load current oscillation with the CMOS output configuration
When the voltage applied at power supply, release operations commence and the detector's output voltage increases.
Load current (I
OUT
) will flow at R
L
. Because a voltage drop (R
IN
x I
OUT
) is produced at the R
IN
resistor, located between
the power supply and the V
IN
pin, the load current will flow via the IC's V
IN
pin. The voltage drop will also lead to a fall in
the voltage level at the V
IN
pin. When the V
IN
pin voltage level falls below the detect voltage level, detect operations will
commence. Following detect operations, load current flow will cease and since voltage drop at R
IN
will disappear, the
voltage level at the V
IN
pin will rise and release operations will begin over again.
Oscillation may occur with this "release - detect - release" repetition.
Further, this condition will also appear via means of a similar mechanism during detect operations.
(2) Oscillation as a result of through current
Since the XC61G series are CMOS IC
S
, through current will flow when the IC's internal circuit switching operates (during
release and detect operations). Consequently, oscillation is liable to occur as a result of drops in voltage at the through
current's resistor (R
IN
) during release voltage operations. (refer to Figure 3 )
Since hysteresis exists during detect operations, oscillation is unlikely to occur.
Power supply
Power supply
5/16
