Freescale Semiconductor
Advance Information
Document Number: MPC7455ECS02AD
Rev. 1.2, 10/2005
MPC7455 RISC Microprocessor
Hardware Specifications Addendum
for the XPC74n5RXnnnNx Series
This document describes part-number-specific changes to
recommended operating conditions and revised electrical
specifications, as applicable, from those described in the
general
MPC7455 RISC Microprocessor Hardware
Specifications
(Order No. MPC7455EC). The MPC7455 is a
PowerPC™ microprocessor.
Specifications provided in this document supersede those in
the
MPC7455 RISC Microprocessor Hardware
Specifications,
Rev. 0 or later, for the part numbers listed in
Table A
only. Specifications not addressed herein are
unchanged. Because this document is frequently updated,
refer to http://www.freescale.com or contact your Freescale
sales office for the latest version.
Note that headings and table numbers in this document are
not consecutively numbered. They are intended to
correspond to the heading or table affected in the general
hardware specification.
Freescale Part Numbers Affected:
XPC7455RX600NC
XPC7455RX733NC
XPC7455RX800NC
XPC7445RX600NC
XPC7445RX733NC
XPC7445RX800NC
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.
Part numbers addressed in this document are listed in
Table A.
Table A. Part Numbers Addressed by This Data Sheet
Operating Conditions
Freescale
Part Number
CPU
Frequency
(MHz)
600
733
800
600
733
800
T
j
(°C)
0 to 105
Significant Differences from
Hardware Specification
V
DD
1.3 V ± 50 mV
XPC7455RX600NC
XPC7455RX733NC
XPC7455RX800NC
XPC7445RX600NC
XPC7445RX733NC
XPC7445RX800NC
Modified core and VCO frequency, and power
consumption specifications
Note:
The X prefix in a Freescale part number designates a “Pilot Production Prototype” as defined by Freescale SOP 3-13.
These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology
to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production
prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging
the qualification status and the fact that product changes may still occur while shipping pilot production prototypes.
1.1 Features
This section summarizes changes to the features of the MPC7455 described in the
MPC7455 RISC
Microprocessor Hardware Specifications.
• Power management
— 1.3-V processor core
1.3 General Parameters
•
Core power supply: 1.3 V ± 50 mV DC nominal
1.5.1 DC Electrical Characteristics
Table 4
provides the recommended operating conditions for the MPC7455 part numbers described herein.
Table 4. Recommended Operating Conditions
Characteristic
Core supply voltage
PLL supply voltage
Symbol
V
DD
AV
DD
Recommended
Value
1.3 V ± 50 mV
1.3 V ± 50 mV
Unit
V
V
Note:
These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not
guaranteed.
MPC7455 RISC Microprocessor Hardware Specifications Addendum for the XPC74n5RXnnnNx Series, Rev. 1.2
2
Freescale Semiconductor
Table 7
provides the power consumption for the MPC7455 part numbers described herein.
Table 7. Power Consumption for MPC7455
Processor (CPU) Frequency
Unit
600 MHz
733 MHz
800 MHz
Notes
Full-Power Mode
Typical
Maximum
8.4
11.9
Doze Mode
Typical
—
Nap Mode
Typical
1.4
Sleep Mode
Typical
700
800
900
mW
1, 2
1.7
1.8
W
1, 2
—
—
W
1, 2, 4
10.3
14.5
11.2
15.9
W
W
1, 3
1, 2
Deep Sleep Mode (PLL Disabled)
Typical
470
490
500
mW
1, 3
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OV
DD
and
GV
DD
) or PLL supply power (AV
DD
). OV
DD
and GV
DD
power is system dependent, but is typically < 5% of V
DD
power. Worst
case power consumption for AV
DD
< 3 mW.
2. Maximum power is measured at nominal V
DD
while running an entirely cache-resident, contrived sequence of instructions
which keep the execution units, with or without AltiVec™, maximally busy.
3. Typical power is an average value measured at nominal V
DD
in a system while running a typical code sequence.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a
result, power consumption for this mode is not tested.
MPC7455 RISC Microprocessor Hardware Specifications Addendum for the XPC74n5RXnnnNx Series, Rev. 1.2
Freescale Semiconductor
3
Table 8
provides the clock AC timing specifications for the MPC7455 part numbers described herein.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See
Table 4.
Maximum Processor Core Frequency
Characteristic
Symbol
600 MHz
Min
Processor frequency
VCO frequency
f
core
f
VCO
500
1000
Max
600
1200
733 MHz
Min
500
1000
Max
733
1466
800 MHz
Min
500
1000
Max
800
1600
MHz
MHz
1
1
Unit
Notes
Note:
1.
Caution:
The SYSCLK frequency, PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) frequency,
CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies
(see Table 4 in the
MPC7455 RISC Microprocessor Hardware Specifications).
Refer to the PLL_CFG[0:4] signal description
in
Section 1.9.1, “PLL Configuration,”
for valid PLL_CFG[0:4] settings.
Table 12
provides the L3 bus interface AC timing specifications for MSUG2 for the MPC7455 part
numbers described herein.
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2
At recommended operating conditions. See
Table 4.
All Speed Grades
Parameter
Symbol
L2CR[12] = 0 and L3CR[12] = 0
8
Min
L3_CLK rise and fall
time
Setup times:
Data and parity
Input hold times:
Data and parity
Valid times:
Data and parity
Valid times:
All other outputs
Output hold times:
Data and parity
Output hold times:
All other outputs
L3_CLK to high
impedance:
Data and parity
t
L3CR
,
t
L3CF
t
L3DVEH
,
t
L3DVEL
t
L3DXEH
,
t
L3DXEL
t
L3CHDV
,
t
L3CLDV
t
L3CHOV
t
L3CHDX
,
t
L3CLDX
t
L3CHOX
t
L3CLDZ
—
–0.1
t
L3_ECHO_CLK
/4
+ 0.6
—
—
t
L3_CLK
/4 – 0.4
t
L3_CLK
/4 – 0.5
—
Max
1.0
—
—
(– t
L3_CLK
/4)
+ 0.4
t
L3_CLK
/4 + 1.0
—
—
t
L3_CLK
/2
L2CR[12] = 1 and L3CR[12] = 1
8
Min
—
–0.1
t
L3_ECHO_CLK
/4
+0.6
—
—
t
L3_CLK
/4 – 0.2
t
L3_CLK
/4 – 0.3
—
Max
1.0
—
—
(– t
L3_CLK
/4)
+ 0.8
t
L3_CLK
/4 + 1.2
—
—
t
L3_CLK
/2
ns
ns
ns
ns
ns
ns
ns
ns
1
2, 3, 4
2, 4
5, 6, 7
5, 7
5, 6, 7
5, 7
Unit
Notes
MPC7455 RISC Microprocessor Hardware Specifications Addendum for the XPC74n5RXnnnNx Series, Rev. 1.2
4
Freescale Semiconductor
Table 12. L3 Bus Interface AC Timing Specifications for MSUG2 (continued)
At recommended operating conditions. See
Table 4.
All Speed Grades
Parameter
Symbol
L2CR[12] = 0 and L3CR[12] = 0
8
Min
L3_CLK to high
impedance:
All other outputs
t
L3CHOZ
—
Max
t
L3_CLK
/4 + 2.0
L2CR[12] = 1 and L3CR[12] = 1
8
Min
—
Max
t
L3_CLK
/4 + 2.0
ns
Unit
Notes
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
DD
.
2. For DDR, all input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising
or falling edge of the input L3_ECHO_CLKn (see Figure 10 in the
MPC7455 RISC Microprocessor Hardware Specifications).
Input timings are measured at the pins.
3. For DDR, the input data will typically follow the edge of L3_ECHO_CLKn as shown in Figure 10 in the
MPC7455 RISC
Microprocessor Hardware Specifications.
For consistency with other input setup time specifications, this will be treated as
negative input setup time.
4. t
L3_ECHO_CLK
/4 is one-fourth the period of L3_ECHO_CLK
n.
This parameter indicates that the MPC7455 can latch an input
signal that is valid for only a short time before and a short time after the midpoint between the rising and falling (or falling and
rising) edges of L3_ECHO_CLKn at any frequency.
5. All output specifications are measured from the midpoint voltage of the rising (or for DDR write data, also the falling) edge of
L3_CLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a
purely resistive 50-Ω load (see Figure 8 in the
MPC7455 RISC Microprocessor Hardware Specifications).
6. For DDR, the output data will typically lead the edge of L3_CLKn as shown in Figure 10 in the
MPC7455 RISC
Microprocessor Hardware Specifications.
For consistency with other output valid time specifications, this will be treated as
negative output valid time.
7. t
L3_CLK
/4 is one-fourth the period of L3_CLKn. This parameter indicates that the specified output signal is actually launched
by an internal clock delayed in phase by 90°. Therefore, there is a frequency component to the output valid and output hold
times such that the specified output signal will be valid for approximately one L3_CLK period starting three-fourths of a clock
prior to the edge on which the SRAM will sample it and ending one-fourth of a clock period after the edge it will be sampled.
8. These configuration bits allow the AC timing of the L3 interface to be altered via software. They must be both set or both
cleared; other configurations will increase t
L3CSKW1
, which may cause unreliable L3 operation.
MPC7455 RISC Microprocessor Hardware Specifications Addendum for the XPC74n5RXnnnNx Series, Rev. 1.2
Freescale Semiconductor
5
电源技术
