Xilinx® 7 series FPGAs comprise four FPGA families that address the complete range of system requirements, ranging from low cost, small form factor,
cost-sensitive, high-volume applications to ultra high-end connectivity bandwidth, logic capacity, and signal processing capability for the most demanding
high-performance applications. The 7 series FPGAs include:
•
Spartan®-7 Family: Optimized for low cost, lowest power, and high
I/O performance. Available in low-cost, very small form-factor
packaging for smallest PCB footprint.
Artix®-7 Family: Optimized for low power applications requiring serial
transceivers and high DSP and logic throughput. Provides the lowest
total bill of materials cost for high-throughput, cost-sensitive
applications.
•
Kintex®-7 Family: Optimized for best price-performance with a 2X
improvement compared to previous generation, enabling a new class
of FPGAs.
Virtex®-7 Family: Optimized for highest system performance and
capacity with a 2X improvement in system performance. Highest
capability devices enabled by stacked silicon interconnect (SSI)
technology.
•
•
Built on a state-of-the-art, high-performance, low-power (HPL), 28 nm, high-k metal gate (HKMG) process technology, 7 series FPGAs enable an
unparalleled increase in system performance with 2.9 Tb/s of I/O bandwidth, 2 million logic cell capacity, and 5.3 TMAC/s DSP, while consuming 50% less
power than previous generation devices to offer a fully programmable alternative to ASSPs and ASICs.
Summary of 7 Series FPGA Features
•
•
•
•
•
•
Advanced high-performance FPGA logic based on real 6-input look-
up table (LUT) technology configurable as distributed memory.
36 Kb dual-port block RAM with built-in FIFO logic for on-chip data
buffering.
High-performance SelectIO™ technology with support for DDR3
interfaces up to 1,866 Mb/s.
High-speed serial connectivity with built-in multi-gigabit transceivers
from 600 Mb/s to max. rates of 6.6 Gb/s up to 28.05 Gb/s, offering a
special low-power mode, optimized for chip-to-chip interfaces.
A user configurable analog interface (XADC), incorporating dual
12-bit 1MSPS analog-to-digital converters with on-chip thermal and
supply sensors.
DSP slices with 25 x 18 multiplier, 48-bit accumulator, and pre-adder
for high-performance filtering, including optimized symmetric
in the United States and other countries. PCI Express is a trademark of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS180 (v2.6) February 27, 2018
Product Specification
www.xilinx.com
1
7 Series FPGAs Data Sheet: Overview
Spartan-7 FPGA Feature Summary
Table 2:
Spartan-7 FPGA Feature Summary by Device
CLB
Device
Logic
Cells
Slices
(1)
938
2,000
3,650
8,150
12,000
16,000
Max
Distributed
RAM (Kb)
70
150
313
600
832
1,100
DSP
Slices
(2)
Block RAM Blocks
(3)
18 Kb
10
20
90
150
180
240
36 Kb
5
10
45
75
90
120
Max
(Kb)
180
360
1,620
2,700
3,240
4,320
CMTs
(4)
PCIe
GT
XADC
Blocks
Total I/O
Banks
(5)
Max User
I/O
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
6,000
12,800
23,360
52,160
76,800
102,400
10
20
80
120
140
160
2
2
3
5
8
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
2
2
3
5
8
8
100
100
150
250
400
400
Notes:
1.
2.
3.
4.
5.
Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
Each CMT contains one MMCM and one PLL.
Does not include configuration Bank 0.
Table 3:
Spartan-7 FPGA Device-Package Combinations and Maximum I/Os
Package
Size (mm)
Ball Pitch (mm)
Device
XC7S6
XC7S15
XC7S25
XC7S50
XC7S75
XC7S100
CPGA196
8x8
0.5
HR I/O
(1)
100
100
CSGA225
13 x 13
0.8
HR I/O
(1)
100
100
150
150
210
CSGA324
15 x 15
0.8
HR I/O
(1)
FTGB196
15 x 15
1.0
HR I/O
(1)
100
100
100
100
250
338
338
400
400
FGGA484
23 x 23
1.0
HR I/O
(1)
FGGA676
27 x 27
1.0
HR I/O
(1)
Notes:
1.
HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.
DS180 (v2.6) February 27, 2018
Product Specification
www.xilinx.com
2
7 Series FPGAs Data Sheet: Overview
Artix-7 FPGA Feature Summary
Table 4:
Artix-7 FPGA Feature Summary by Device
Configurable Logic Blocks
(CLBs)
Device
Logic
Cells
Slices
(1)
2,000
2,600
3,650
5,200
8,150
11,800
15,850
33,650
Max
Distributed
RAM (Kb)
171
200
313
400
600
892
1,188
2,888
DSP48E1
Slices
(2)
18 Kb
40
45
80
90
120
180
240
740
40
50
90
100
150
210
270
730
36 Kb
20
25
45
50
75
105
135
365
Block RAM Blocks
(3)
CMTs
(4)
Max
(Kb)
720
900
1,620
1,800
2,700
3,780
4,860
13,140
3
5
3
5
5
6
6
10
1
1
1
1
1
1
1
1
2
4
4
4
4
8
8
16
PCIe
(5)
GTPs
XADC
Blocks
Total I/O
Banks
(6)
Max User
I/O
(7)
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
12,800
16,640
23,360
33,280
52,160
75,520
101,440
215,360
1
1
1
1
1
1
1
1
3
5
3
5
5
6
6
10
150
250
150
250
250
300
300
500
Notes:
1.
Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
2.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
4.
Each CMT contains one MMCM and one PLL.
5.
Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.
6.
Does not include configuration Bank 0.
7.
This number does not include GTP transceivers.
Table 5:
Artix-7 FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7A12T
XC7A15T
XC7A25T
XC7A35T
XC7A50T
XC7A75T
XC7A100T
XC7A200T
2
2
106
106
2
106
2
112
0
0
0
0
210
210
210
210
GTP
(4)
CPG236
10 x 10
0.5
I/O
HR
(5)
CPG238
10 x 10
0.5
GTP
(4)
CSG324
15 x 15
0.8
CSG325
15 x 15
0.8
FTG256
17 x 17
1.0
SBG484
19 x 19
0.8
FGG484
(2)
23 x 23
1.0
FBG484
(2)
23 x 23
1.0
FGG676
(3)
27 x 27
1.0
FBG676
(3)
27 x 27
1.0
FFG1156
35 x 35
1.0
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
(4)
I/O
HR
(5)
GTP
I/O
HR
(5)
GTP
I/O
HR
(5)
2
112
0
210
2
4
4
4
4
150
150
150
150
150
0
0
0
0
170
170
170
170
4
285
4
4
4
4
250
250
285
285
4
285
8
8
300
300
8
400
16
500
0
170
4
250
Notes:
1.
All packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.
2.
Devices in FGG484 and FBG484 are footprint compatible.
3.
Devices in FGG676 and FBG676 are footprint compatible.
4.
GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25 Gb/s.
5.
HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.
DS180 (v2.6) February 27, 2018
Product Specification
www.xilinx.com
3
7 Series FPGAs Data Sheet: Overview
Kintex-7 FPGA Feature Summary
Table 6:
Kintex-7 FPGA Feature Summary by Device
Configurable Logic
Blocks (CLBs)
Device
Logic
Cells
Slices
(1)
10,250
25,350
50,950
55,650
63,550
65,150
74,650
Max
Distributed
RAM (Kb)
838
2,188
4,000
5,088
5,663
5,938
6,788
DSP
Slices
(2)
18 Kb
240
600
840
1,440
1,540
1,680
1,920
270
650
890
1,430
1,590
1,670
1,910
36 Kb
135
325
445
715
795
835
955
Max (Kb)
4,860
11,700
16,020
25,740
28,620
30,060
34,380
6
8
10
6
10
8
8
1
1
1
1
1
1
1
8
8
16
24
16
32
32
1
1
1
1
1
1
1
6
8
10
6
10
8
8
Block RAM Blocks
(3)
CMTs
(4)
PCIe
(5)
GTXs
XADC
Blocks
Total I/O
Banks
(6)
Max
User
I/O
(7)
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
65,600
162,240
326,080
356,160
406,720
416,960
477,760
300
400
500
300
500
400
400
Notes:
1.
Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
2.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
3.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
4.
Each CMT contains one MMCM and one PLL.
5.
Kintex-7 FPGA Interface Blocks for PCI Express support up to x8 Gen 2.
6.
Does not include configuration Bank 0.
7.
This number does not include GTX transceivers.
Table 7:
Kintex-7 FPGA Device-Package Combinations and Maximum I/Os
Package
(1)
Size (mm)
Ball Pitch
(mm)
Device
XC7K70T
XC7K160T
XC7K325T
XC7K355T
XC7K410T
XC7K420T
XC7K480T
8
250
150
8
250
150
16
350
150
16
350
150
28
28
380
380
0
0
32
32
400
400
0
0
GTX
(4)
FBG484
23 x 23
1.0
I/O
HR
(5)
HP
(6)
185
185
100
100
GTX
(4)
FBG676
(2)
27 x 27
1.0
I/O
HR
(5)
HP
(6)
200
250
250
100
150
150
8
8
GTX
FFG676
(2)
27 x 27
1.0
I/O
HR
(5)
HP
(6)
GTX
(4)
FBG900
(3)
31 x 31
1.0
I/O
HR
(5)
HP
(6)
GTX
FFG900
(3)
31 x 31
1.0
I/O
HR
(5)
HP
(6)
GTX
FFG901
31 x 31
1.0
I/O
HR
(5)
HP
(6)
GTX
FFG1156
35 x 35
1.0
I/O
HR
(5)
HP
(6)
4
4
8
8
8
250
250
150
150
16
350
150
16
350
150
24
300
0
Notes:
1.
All packages listed are Pb-free (FBG, FFG with exemption 15). Some packages are available in Pb option.
2.
Devices in FBG676 and FFG676 are footprint compatible.
3.
Devices in FBG900 and FFG900 are footprint compatible.
4.
GTX transceivers in FB packages support the following maximum data rates: 10.3Gb/s in FBG484; 6.6Gb/s in FBG676 and FBG900. Refer to
Kintex-7 FPGAs Data Sheet:
DC and AC Switching Characteristics
(DS182) for details.
5.
HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.
6.
HP = High-performance I/O with support for I/O voltage from 1.2V to 1.8V.
DS180 (v2.6) February 27, 2018
Product Specification
www.xilinx.com
4
7 Series FPGAs Data Sheet: Overview
Virtex-7 FPGA Feature Summary
Table 8:
Virtex-7 FPGA Feature Summary
Configurable Logic
Blocks (CLBs)
Device
(1)
Logic
Cells
Slices
(2)
91,050
305,400
51,000
64,400
75,900
86,600
108,300
153,000
178,000
90,700
136,900
Max
Distributed
RAM (Kb)
6,938
21,550
4,388
6,525
8,175
8,725
10,888
13,838
17,700
8,850
13,275
DSP
Slices
(3)
18 Kb
1,260
2,160
1,120
2,160
2,800
2,880
3,600
3,600
3,360
1,680
2,520
1,590
2,584
1,500
1,760
2,060
2,360
2,940
3,000
3,760
1,880
2,820
36 Kb
795
1,292
750
880
1,030
1,180
1,470
1,500
1,880
940
1,410
Block RAM Blocks
(4)
CMTs
Max
(Kb)
28,620
46,512
27,000
31,680
37,080
42,480
52,920
54,000
67,680
33,840
50,760
(5)
PCIe
(6)
GTX
GTH
GTZ
XADC
Blocks
Total I/O
Banks
(7)
Max
User
I/O
(8)
SLRs
(9)
XC7V585T
XC7V2000T
XC7VX330T
XC7VX415T
XC7VX485T
XC7VX550T
XC7VX690T
XC7VX980T
XC7VX1140T
XC7VH580T
XC7VH870T
582,720
1,954,560
326,400
412,160
485,760
554,240
693,120
979,200
1,139,200
580,480
876,160
18
24
14
12
14
20
20
18
24
12
18
3
4
2
2
4
2
3
3
4
2
3
36
36
0
0
56
0
0
0
0
0
0
0
0
28
48
0
80
80
72
96
48
72
0
0
0
0
0
0
0
0
0
8
16
1
1
1
1
1
1
1
1
1
1
1
17
24
14
12
14
16
20
18
22
12
6
850
1,200
700
600
700
600
1,000
900
1,100
600
300
N/A
4
N/A
N/A
N/A
N/A
N/A
N/A
4
2
3
Notes:
1.
EasyPath™-7 FPGAs are also available to provide a fast, simple, and risk-free solution for cost reducing Virtex-7 T and Virtex-7 XT FPGA designs
2.
Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.
3.
Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.
4.
Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.
5.
Each CMT contains one MMCM and one PLL.
6.
Virtex-7 T FPGA Interface Blocks for PCI Express support up to x8 Gen 2. Virtex-7 XT and Virtex-7 HT Interface Blocks for PCI Express support up to x8 Gen 3, with the
exception of the XC7VX485T device, which supports x8 Gen 2.
7.
Does not include configuration Bank 0.
8.
This number does not include GTX, GTH, or GTZ transceivers.
9.
Super logic regions (SLRs) are the constituent parts of FPGAs that use SSI technology. Virtex-7 HT devices use SSI technology to connect SLRs with 28.05 Gb/s
- startup_stm32f10x_ld_vl.s: for STM32 Low density Value line devices - startup_stm32f10x_ld.s: for STM32 Low density devices - startup_stm32f10x_md_vl.s: for STM32 Medium density Value line devices -...[详细]
RF/无线
