XC7SET125
Bus buffer/line driver; 3-state
Rev. 01 — 4 September 2009
Product data sheet
1. General description
XC7SET125 is a high-speed Si-gate CMOS devices. It provides one non-inverting
buffer/line driver with 3-state output. The 3-state output is controlled by the output enable
input (OE). A HIGH at OE causes the output to assume a high-impedance OFF-state.
2. Features
I
I
I
I
I
I
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
SOT353-1 and SOT753 package options
ESD protection:
N
HBM JESD22-A114E: exceeds 2000 V
N
MM JESD22-A115-A: exceeds 200 V
N
CDM JESD22-C101C: exceeds 1000 V
I
Specified from
−40 °C
to +125
°C
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
XC7SET125GW
XC7SET125GV
XC7SET125GM
−40 °C
to +125
°C
XC7SET125GF
XSON6
−40 °C
to +125
°C
−40 °C
to +125
°C
−40 °C
to +125
°C
Name
TSSOP5
SC-74A
XSON6
Description
plastic thin shrink small outline package;
5 leads; body width 1.25 mm
plastic surface-mounted package; 5 leads
Version
SOT353-1
SOT753
Type number
plastic extremely thin small outline package; no SOT886
leads; 6 terminals; body 1
×
1.45
×
0.5 mm
plastic extremely thin small outline package;
no leads; 6 terminals; body 1
×
1
×
0.5 mm
SOT891
NXP Semiconductors
XC7SET125
Bus buffer/line driver; 3-state
4. Marking
Table 2.
Marking codes
Marking
[1]
gM
g25
gM
gM
Type number
XC7SET125GW
XC7SET125GV
XC7SET125GM
XC7SET125GF
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
2
A
Y
4
2
4
A
1
Y
1
OE
mna118
EN
mna119
OE
mna120
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
Fig 3.
Logic diagram
6. Pinning information
6.1 Pinning
XC7SET125
XC7SET125
OE
A
1
2
GND
GND
3
001aak126
OE
5
V
CC
1
6
V
CC
OE
A
XC7SET125
1
2
3
6
5
4
V
CC
n.c.
Y
A
2
5
n.c.
3
4
Y
GND
4
Y
001aak127
001aak128
Transparent top view
Transparent top view
Fig 4.
Pin configuration
SOT353-1 and SOT753
Fig 5.
Pin configuration SOT886
Fig 6.
Pin configuration SOT891
XC7SET125_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 4 September 2009
2 of 14
NXP Semiconductors
XC7SET125
Bus buffer/line driver; 3-state
6.2 Pin description
Table 3.
Symbol
OE
A
GND
Y
n.c.
V
CC
Pin description
Pin
SOT353-1/SOT753
1
2
3
4
-
5
SOT886/SOT891
1
2
3
4
5
6
output enable input
data input
ground (0 V)
data output
not connected
supply voltage
Description
7. Functional description
Table 4.
Function table
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state
Inputs
OE
L
L
H
A
L
H
X
Output
Y
L
H
Z
8. Limiting values
Table 5.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
Min
−0.5
−0.5
Max
+7.0
+7.0
-
±20
±25
75
-
+150
250
Unit
V
V
mA
mA
mA
mA
mA
°C
mW
V
I
<
−0.5
V
V
O
<
−0.5
V or V
O
> V
CC
+ 0.5 V
−0.5
V < V
O
< V
CC
+ 0.5 V
[1]
[1]
−20
-
-
-
−75
−65
T
amb
=
−40 °C
to +125
°C
[2]
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For TSSOP5 and SC-74A packages: above 87.5
°C
the value of P
tot
derates linearly with 4.0 mW/K.
For XSON6 packages: above 118
°C
the value of P
tot
derates linearly with 7.8 mW/K.
XC7SET125_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 4 September 2009
3 of 14
NXP Semiconductors
XC7SET125
Bus buffer/line driver; 3-state
9. Recommended operating conditions
Table 6.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
CC
V
I
V
O
T
amb
∆t/∆V
supply voltage
input voltage
output voltage
ambient temperature
input transition rise and fall rate
Conditions
Min
4.5
0
0
−40
-
Typ
5.0
-
-
+25
-
Max
5.5
5.5
V
CC
+125
20
Unit
V
V
V
°C
ns/V
10. Static characteristics
Table 7.
Static characteristics
Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
V
IL
V
OH
HIGH-level
input voltage
LOW-level
input voltage
Conditions
Min
V
CC
= 4.5 V to 5.5 V
V
CC
= 4.5 V to 5.5 V
2.0
-
25
°C
Typ
-
-
Max
-
0.8
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
2.0
-
Max
-
0.8
Min
2.0
-
Max
-
0.8
V
V
HIGH-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
=
−50 µA
I
O
=
−8.0
mA
LOW-level
V
I
= V
IH
or V
IL
; V
CC
= 4.5 V
output voltage
I
O
= 50
µA
I
O
= 8.0 mA
OFF-state
V
I
= V
CC
or GND;
output current V
CC
= 5.5 V
input leakage
current
V
I
= 5.5 V or GND;
V
CC
= 0 V to 5.5 V
4.4
3.94
-
-
-
-
-
-
4.5
-
0
-
-
-
-
-
-
-
0.1
0.36
0.25
0.1
1.0
1.35
4.4
3.8
-
-
-
-
-
-
-
-
0.1
0.44
2.5
1.0
10
1.5
4.4
3.70
-
-
-
-
-
-
-
-
0.1
0.55
10
2.0
40
1.5
V
V
V
V
µA
µA
µA
mA
V
OL
I
OZ
I
I
I
CC
∆I
CC
supply current V
I
= V
CC
or GND; I
O
= 0 A;
V
CC
= 5.5 V
additional
per input pin; V
I
= 3.4 V;
supply current other inputs at V
CC
or GND;
I
O
= 0 A; V
CC
= 5.5 V
input
capacitance
C
I
-
1.5
10
-
10
-
10
pF
XC7SET125_1
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 4 September 2009
4 of 14
NXP Semiconductors
XC7SET125
Bus buffer/line driver; 3-state
11. Dynamic characteristics
Table 8.
Dynamic characteristics
GND = 0 V; For test circuit see
Figure 9.
Symbol Parameter
t
pd
propagation
delay
Conditions
Min
A to Y; see
Figure 7
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
t
en
enable time
OE to Y; see
Figure 8
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
t
dis
disable time
OE to Y; see
Figure 8
V
CC
= 4.5 V to 5.5 V
C
L
= 15 pF
C
L
= 50 pF
C
PD
power
per buffer;
dissipation
C
L
= 50 pF; f = 1 MHz;
capacitance V
I
= GND to V
CC
t
pd
is the same as t
PLH
and t
PHL
.
t
en
is the same as t
PZL
and t
PZH
.
t
dis
is the same as t
PLZ
and t
PHZ
.
[2]
[3]
Typical values are measured at V
CC
= 5.0 V.
C
PD
is used to determine the dynamic power dissipation P
D
(µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
[3]
[1]
[2]
[1]
[2]
[1]
[2]
25
°C
Typ
Max
−40 °C
to +85
°C −40 °C
to +125
°C
Unit
Min
Max
Min
Max
-
-
3.4
4.8
5.5
7.5
1.0
1.0
6.5
8.5
1.0
1.0
7.0
9.5
ns
ns
-
-
3.9
5.1
5.1
7.5
1.0
1.0
6.0
8.5
1.0
1.0
6.5
9.5
ns
ns
-
-
-
4.5
6.1
11
6.8
8.8
-
1.0
1.0
-
8.0
10.0
-
1.0
1.0
-
8.5
11.0
-
ns
ns
pF
[1]
12. Waveforms
V
I
A input
GND
t
PHL
V
OH
Y output
V
OL
V
M
mnb153
V
M
t
PLH
Measurement points are given in
Table 9.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 7.
XC7SET125_1
Input (A) to output (Y) propagation delays
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 01 — 4 September 2009
5 of 14
FPGA/CPLD
