Product Obsolete/Under Obsolescence
0
R
XC95216 In-System
Programmable CPLD
0
5
DS068 (v5.0) May 17, 2013
Product Specification
Features
•
•
•
•
•
10 ns pin-to-pin logic delays on all pins
f
CNT
to 111 MHz
216 macrocells with 4,800 usable gates
Up to 166 user I/O pins
5V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full commercial voltage and
temperature range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables,
set and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design
protection
High-drive 24 mA outputs
3.3V or 5V I/O capability
Advanced CMOS 5V FastFLASH™ technology
Supports parallel programming of more than one
XC9500 concurrently
Available 160-pin PQFP, 352-pin BGA, and 208-pin
HQFP packages (Note: 352-pin BGA packages are
being discontinued for this device)
Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See
Figure 2
for the architec-
ture overview.
Power Management
Power dissipation can be reduced in the XC95216 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
I
CC
(mA) = MC
HP
(1.7) + MC
LP
(0.9) + MC (0.006 mA/MHz) f
Where:
MC
HP
= Macrocells in high-performance mode
MC
LP
= Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1
shows a typical calculation for the XC95216
device.
600
•
•
•
•
•
•
•
•
•
•
•
•
High
man
Perfor
ce
(500)
Typical I
CC
(mA)
400
(360)
(340)
Low P
200
ower
0
50
100
DS068_01_110101
Clock Frequency (MHz)
Figure 1:
Typical I
CC
vs. Frequency for XC95216
© 1998–2007, 2013 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS068 (v5.0) May 17, 2013
Product Specification
www.xilinx.com
1
Product Obsolete/Under Obsolescence
R
XC95216 In-System Programmable CPLD
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
36
I/O
I/O
I/O
Fast CONNECT II Switch Matrix
I/O
36
18
18
Function
Block 1
Macrocells
1 to 18
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
1
I/O/GSR
2
I/O/GTS
36
18
Function
Block 3
Macrocells
1 to 18
36
18
Function
Block 4
Macrocells
1 to 18
36
18
Function
Block 12
Macrocells
1 to 18
DS068_02_110101
Figure 2:
XC95216 Architecture
Function block outputs (indicated by the bold line) drive the I/O blocks directly.
DS068 (v5.0) May 17, 2013
Product Specification
www.xilinx.com
2
Product Obsolete/Under Obsolescence
R
XC95216 In-System Programmable CPLD
Absolute Maximum Ratings
Symbol
V
CC
V
IN
V
TS
T
STG
T
J
Description
Supply voltage relative to GND
Input voltage relative to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Junction temperature
Value
–0.5 to 7.0
–0.5 to V
CC
+ 0.5
–0.5 to V
CC
+ 0.5
–65 to +150
+150
Units
V
V
V
o
C
o
C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol
V
CCINT
V
CCIO
Parameter
Supply voltage for internal logic
and input buffers
Supply voltage for output drivers
for 5V operation
Commercial T
A
= 0
o
C to 70
o
C
Industrial T
A
= –40
o
C to +85
o
C
Commercial T
A
= 0
o
C to 70
o
C
Industrial T
A
= –40
o
C to +85
o
C
Min
4.75
4.5
4.75
4.5
3.0
0
2.0
0
Max
5.25
5.5
5.25
5.5
3.6
0.80
V
CCINT
+ 0.5
V
CCIO
V
V
V
V
Units
V
Supply voltage for output drivers for 3.3V operation
V
IL
V
IH
V
O
Low-level input voltage
High-level input voltage
Output voltage
Quality and Reliability Characteristics
Symbol
T
DR
N
PE
Data Retention
Program/Erase Cycles (Endurance)
Parameter
Min
20
10,000
Max
-
-
Units
Years
Cycles
DC Characteristic Over Recommended Operating Conditions
Symbol
V
OH
V
OL
I
IL
I
IH
C
IN
I
CC
Parameter
Output high voltage for 5V outputs
Output high voltage for 3.3V outputs
Output low voltage for 5V outputs
Output low voltage for 3.3V outputs
Input leakage current
I/O high-Z leakage current
I/O capacitance
Operating supply current
(low power mode, active)
Test Conditions
I
OH
= –4.0 mA, V
CC
= Min
I
OH
= –3.2 mA, V
CC
= Min
I
OL
= 24 mA, V
CC
= Min
I
OL
= 10 mA, V
CC
= Min
V
CC
= Max
V
IN
= GND or V
CC
V
CC
= Max
V
IN
= GND or V
CC
V
IN
= GND
f = 1.0 MHz
V
I
= GND, No load
f = 1.0 MHz
Min
2.4
2.4
-
-
-
-
-
Max
-
-
0.5
0.4
±10
±10
10
Units
V
V
V
V
μA
μA
pF
mA
200 (Typical)
DS068 (v5.0) May 17, 2013
Product Specification
www.xilinx.com
3
Product Obsolete/Under Obsolescence
R
XC95216 In-System Programmable CPLD
AC Characteristics
XC95216-10
Symbol
T
PD
T
SU
T
H
T
CO
f
CNT(1)
T
PSU
T
PH
T
PCO
T
OE
T
OD
T
POE
T
POD
T
WLH
T
APRPW
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
16-bit counter frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GCK pulse width (High or Low)
Asynchronous preset/reset pulse width (High
or Low)
Min
-
6.0
0
-
111.1
66.7
2.0
4.0
-
-
-
-
-
4.5
7.5
Max
10.0
-
-
6.0
-
-
-
-
10.0
6.0
6.0
10.0
10.0
-
-
XC95216-15
Min
-
8.0
0
-
95.2
55.6
4.0
4.0
-
-
-
-
-
5.5
8.0
Max
15.0
-
-
8.0
-
-
-
-
12.0
11.0
11.0
14.0
14.0
-
-
XC95216-20
Min
-
10.0
0
-
83.3
50.0
4.0
6.0
-
-
-
-
-
5.5
8.0
Max
20.0
-
-
10.0
-
-
-
-
16.0
16.0
16.0
18.0
18.0
-
-
Units
ns
ns
ns
ns
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
f
SYSTEM(2)
Multiple FB internal operating frequency
Notes:
1. f
CNT
is the fastest 16-bit counter frequency available, using the local feedback when applicable.
f
CNT
is also the Export Control Maximum flip-flop toggle rate, f
TOG
.
2. f
SYSTEM
is the internal operating frequency for general purpose system designs spanning multiple FBs.
V
TEST
R
1
Device Output
R
2
C
L
Output Type
V
CCIO
5.0V
3.3V
V
TEST
5.0V
3.3V
R
1
160Ω
260Ω
R
2
120Ω
360Ω
C
L
35 pF
35 pF
DS067_03_110101
Figure 3:
AC Load Circuit
DS068 (v5.0) May 17, 2013
Product Specification
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4
Product Obsolete/Under Obsolescence
R
XC95216 In-System Programmable CPLD
Internal Timing Parameters
XC95216-10
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
T
PTCK
T
PTSR
T
PTTS
T
PDI
T
SUI
T
HI
T
COI
T
AOI
T
RAI
T
LOGI
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
-
-
-
-
-
-
3.5
2.5
6.0
6.0
3.0
0
-
-
-
-
-
-
4.5
3.0
7.5
11.0
4.5
0
-
-
-
-
-
-
6.5
3.0
9.5
16.0
6.5
0
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
XC95216-15
Min
Max
XC95216-20
Min
Max
Units
Product Term Control Delays
Product term clock delay
Product term set/reset delay
Product term 3-state delay
-
-
-
3.0
2.5
3.5
-
-
-
2.5
3.0
5.0
-
-
-
2.5
3.0
5.0
ns
ns
ns
Internal Register and Combinatorial Delays
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
-
2.5
3.5
-
-
10.0
-
-
1.0
-
-
0.5
7.0
-
2.5
11.0
-
3.5
4.5
-
-
10.0
-
-
3.0
-
-
0.5
8.0
-
3.0
11.5
-
3.5
6.5
-
-
10.0
-
-
4.0
-
-
0.5
8.0
-
3.0
11.5
ns
ns
ns
ns
ns
ns
ns
ns
T
LOGILP
Internal low power logic delay
Feedback Delays
T
F
T
LF
FastCONNECT feedback delay
Function block local feedback delay
-
-
9.5
3.5
-
-
11.0
3.5
-
-
13.0
5.0
ns
ns
Time Adders
T
PTA(1)
Incremental product term allocator delay
T
SLEW
Slew-rate limited delay
-
-
1.0
4.5
-
-
1.0
5.0
-
-
1.5
5.5
ns
ns
Notes:
1. T
PTA
is multiplied by the span of the function as defined in the XC9500 family data sheet.
DS068 (v5.0) May 17, 2013
Product Specification
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5
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