0
R
XC9572XL High Performance
CPLD
0
0
DS057 (v2.0) April 3, 2007
Product Specification
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 5 ns. See
Figure 2
for overview.
Features
•
•
•
•
5 ns pin-to-pin logic delays
System frequency up to 178 MHz
72 macrocells with 1,600 usable gates
Available in small footprint packages
- 44-pin PLCC (34 user I/O pins)
- 44-pin VQFP (34 user I/O pins)
- 48-pin CSP (38 user I/O pins)
- 64-pin VQFP (52 user I/O pins)
- 100-pin TQFP (72 user I/O pins)
- Pb-free available for all packages
Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Pin-compatible with 5V-core XC9572 device in the
44-pin PLCC package and the 100-pin TQFP package
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XL device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
CC
, the following equation may be
used:
I
CC
(mA) = MC
HS
(0.175*PT
HS
+ 0.345) + MC
LP
(0.052*PT
LP
+ 0.272) + 0.04 * MC
TOG
(MC
HS
+MC
LP
)* f
where:
MC
HS
= # macrocells in high-speed configuration
PT
HS
= average number of high-speed product terms
per macrocell
MC
LP
= # macrocells in low power configuration
PT
LP
= average number of low power product terms per
macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XC9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual I
CC
value varies with the design application and should be veri-
fied during normal system operation.
Figure 1
shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
•
•
•
•
•
•
•
WARNING: Programming temperature range of
T
A
= 0° C to +70° C
Description
The XC9572XL is a 3.3V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
© 2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS057 (v2.0) April 3, 2007
Product Specification
www.xilinx.com
1
XC9572XL High Performance CPLD
application note
XAPP114, “Understanding XC9500XL
CPLD Power.”
125
178 MHz
100
Typical ICC (mA)
Hi g
hP
e
ma
rfor
nce
R
75
50
Lo
o
wP
we
r
104 MHz
25
0
50
100
150
200
Clock Frequency (MHz)
DS057_01_010102
Figure 1:
Typical I
CC
vs. Frequency for XC9572XL
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
54
I/O
I/O
I/O
18
Function
Block 1
Macrocells
1 to 18
Fast CONNECT II Switch Matrix
I/O
54
18
Function
Block 2
Macrocells
1 to 18
I/O
Blocks
I/O
I/O
I/O
I/O
3
I/O/GCK
1
I/O/GSR
I/O/GTS
2
54
18
Function
Block 3
Macrocells
1 to 18
54
18
Function
Block 4
Macrocells
1 to 18
DS057_02_082800
Figure 2:
XC9572XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
www.xilinx.com
DS057 (v2.0) April 3, 2007
Product Specification
R
XC9572XL High Performance CPLD
Absolute Maximum Ratings
(2)
Symbol
V
CC
V
IN
V
TS
T
STG
T
J
Description
Supply voltage relative to GND
Input voltage relative to GND
(1)
Voltage applied to 3-state output
(1)
Storage temperature (ambient)
(3)
Junction temperature
Value
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
–65 to +150
+150
Units
V
V
V
o
C
o
C
Notes:
1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed V
CCINT
by 4.0V.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
3. For soldering guidelines and thermal considerations, see the
Device Packaging
information on the Xilinx website. For Pb-free
packages, see
XAPP427.
Recommended Operation Conditions
Symbol
V
CCINT
V
CCIO
V
IL
V
IH
V
O
Parameter
Supply voltage for internal logic
and input buffers
Commercial T
A
= 0
o
C to 70
o
C
Industrial T
A
= –40
o
C to +85
o
C
Min
3.0
3.0
3.0
2.3
0
2.0
0
Max
3.6
3.6
3.6
2.7
0.80
5.5
V
CCIO
Units
V
V
V
V
V
V
V
Supply voltage for output drivers for 3.3V operation
Supply voltage for output drivers for 2.5V operation
Low-level input voltage
High-level input voltage
Output voltage
Quality and Reliability Characteristics
Symbol
T
DR
N
PE
V
ESD
Data Retention
Program/Erase Cycles (Endurance)
Electrostatic Discharge (ESD)
Parameter
Min
20
10,000
2,000
Max
-
-
-
Units
Years
Cycles
Volts
DC Characteristic Over Recommended Operating Conditions
Symbol
V
OH
V
OL
I
IL
I
IH
I
IH
Parameter
Output high voltage for 3.3V outputs
Output high voltage for 2.5V outputs
Output low voltage for 3.3V outputs
Output low voltage for 2.5V outputs
Input leakage current
I/O high-Z leakage current
I/O high-Z leakage current
Test Conditions
I
OH
= –4.0 mA
I
OH
= –500
μA
I
OL
= 8.0 mA
I
OL
= 500
μA
V
CC
= Max; V
IN
= GND or V
CC
V
CC
= Max; V
IN
= GND or V
CC
V
CC
= Max; V
CCIO
= Max;
V
IN
= GND or 3.6V
V
CC
Min < V
IN
< 5.5V
C
IN
I
CC
I/O capacitance
Operating supply current
(low power mode, active)
V
IN
= GND; f = 1.0 MHz
V
IN
= GND, No load; f = 1.0 MHz
Min
2.4
90% V
CCIO
-
-
-
-
-
-
-
20 (Typical)
Max
-
-
0.4
0.4
±10
±10
±10
±50
10
Units
V
V
V
V
μA
μA
μA
μA
pF
mA
DS057 (v2.0) April 3, 2007
Product Specification
www.xilinx.com
3
XC9572XL High Performance CPLD
R
AC Characteristics
XC9572XL-5
Symbol
T
PD
T
SU
T
H
T
CO
f
SYSTEM
T
PSU
T
PH
T
PCO
T
OE
T
OD
T
POE
T
POD
T
AO
T
PAO
T
WLH
T
APRPW
T
PLH
Parameter
I/O to output valid
I/O setup time before GCK
I/O hold time after GCK
GCK to output valid
Multiple FB internal operating frequency
I/O setup time before p-term clock input
I/O hold time after p-term clock input
P-term clock output valid
GTS to output valid
GTS to output disable
Product term OE to output enabled
Product term OE to output disabled
GSR to output valid
P-term S/R to output valid
GCK pulse width (High or Low)
Asynchronous preset/reset pulse width
(High or Low)
P-term clock pulse width (High or Low)
Min
-
3.7
0
-
-
1.7
2.0
-
-
-
-
-
-
-
2.8
5.0
5.0
Max
5.0
-
-
3.5
178.6
-
-
5.5
4.0
4.0
7.0
7.0
10.0
10.5
-
-
-
XC9572XL-7
Min
-
4.8
0
-
-
1.6
3.2
-
-
-
-
-
-
-
4.0
6.5
6.5
Max
7.5
-
-
4.5
125.0
-
-
7.7
5.0
5.0
9.5
9.5
12.0
12.6
-
-
-
XC9572XL-10
Min
-
6.5
0
-
-
2.1
4.4
-
-
-
-
-
-
-
4.5
7.0
7.0
Max
10.0
-
-
5.8
100.0
-
-
10.2
7.0
7.0
11.0
11.0
14.5
15.3
-
-
-
Units
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
TEST
R
1
Device Output
R
2
C
L
Output Type
V
CCIO
3.3V
2.5V
V
TEST
3.3V
2.5V
R
1
320
Ω
250
Ω
R
2
360
Ω
660
Ω
C
L
35 pF
35 pF
DS058_03_081500
Figure 3:
AC Load Circuit
4
www.xilinx.com
DS057 (v2.0) April 3, 2007
Product Specification
R
XC9572XL High Performance CPLD
Internal Timing Parameters
XC9572XL-5
Symbol
Buffer Delays
T
IN
T
GCK
T
GSR
T
GTS
T
OUT
T
EN
T
PTCK
T
PTSR
T
PTTS
T
PDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
LOGI
T
LOGILP
T
F
T
PTA
T
SLEW
Input buffer delay
GCK buffer delay
GSR buffer delay
GTS buffer delay
Output buffer delay
Output buffer enable/disable delay
Product term clock delay
Product term set/reset delay
Product term 3-state delay
Combinatorial logic propagation delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output valid time
Register async. S/R to output delay
Register async. S/R recover before clock
Internal logic delay
Internal low power logic delay
Fast CONNECT II feedback delay
Incremental product term allocator delay
Slew-rate limited delay
-
-
-
-
-
-
-
-
-
-
2.3
1.4
2.4
1.4
-
-
5.0
-
-
-
-
-
1.0
5.0
1.9
0.7
3.0
1.5
1.1
2.0
4.0
2.0
0
1.6
1.0
5.5
0.5
-
-
-
-
0.4
6.0
-
-
-
-
-
-
-
-
-
-
2.6
2.2
2.6
2.2
-
-
7.5
-
-
-
-
-
1.4
6.4
3.5
0.8
4.0
2.3
1.5
3.1
5.0
2.5
0
2.4
1.4
7.2
1.3
-
-
-
-
0.5
6.4
-
-
-
-
-
-
-
-
-
-
3.0
3.5
3.0
3.5
-
-
10.0
-
-
-
-
-
1.8
7.3
4.2
1.0
4.5
3.5
1.8
4.5
7.0
3.0
0
2.7
1.8
7.5
1.7
-
-
-
-
1.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Min
Max
XC9572XL-7
Min
Max
XC9572XL-10
Min
Max
Units
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays
Time Adders
DS057 (v2.0) April 3, 2007
Product Specification
www.xilinx.com
5
