Product Obsolete or Under Obsolescence
X-Ref Target - Figure 0
R
Spartan/XL Family One-Time Programmable
Configuration PROMs (XC17S00/XL)
Product Specification
DS030 (v1.12) June 20, 2008
Features
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan
®
, and Spartan-XL FPGAs
Simple interface to the Spartan device requires only
one user I/O pin
Programmable reset polarity (active High or active Low)
Low-power CMOS floating-gate process
Available in 5V and 3.3V versions
•
•
•
•
•
Available in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC packages
Programming support by leading programmer
manufacturers
Lead-free (RoHS-compliant) packaging available
Design support using the Xilinx
®
Alliance and
Foundation™ series software packages
Guaranteed 20 year life data retention
•
•
•
•
Introduction
The Spartan family of PROMs provides an easy-to-use,
cost-effective method for storing Spartan device
configuration bitstreams.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
FPGA PROM. A short access time after the rising clock
edge, data appears on the PROM DATA output pin that is
connected to the Spartan device D
IN
pin. The Spartan
device generates the appropriate number of clock pulses to
Spartan FPGA
XCS05
XCS05XL
XCS10
XCS10XL
XCS20
XCS20XL
XCS30
XCS30XL
XCS40
XCS40XL
XC2S50
(1)
XC2S100
(1)
XC2S150
(1)
Notes:
1.
For new Spartan-II FPGA designs, it is recommended to use the 17S00A family.
complete the configuration. Once configured, it disables the
PROM. When a Spartan device is in Slave Serial mode, the
PROM and the Spartan device must both be clocked by an
incoming signal.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
Configuration Bits
53,984
54,544
95,008
95,752
178,144
179,160
247,968
249,168
329,312
330,696
559,200
781,216
1,040,096
Compatible Spartan PROM
XC17S05
XC17S05XL
XC17S10
XC17S10XL
XC17S20
XC17S20XL
XC17S30
XC17S30XL
XC17S40
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
© Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS030 (v1.12) June 20, 2008
Product Specification
www.xilinx.com
1
R
Product Obsolete
One-Time Programmable Configuration PROMs (XC17S00/XL)
Spartan/XL Family
or Under Obsolescence
Pin Description
Pins not listed are in
Table 1
are "no connects."
Table 1:
Spartan PROM Pinouts
Pin Name
8-pin
PDIP (PD8) and
VOIC/TSOP (VO8)
1
20-pin
SOIC
(SO20)
1
Pin Description
Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to be either
active High or active Low.
Each rising edge on the CLK input increments the internal address counter, if both
CE and OE are active.
When High, this input holds the address counter reset and puts the DATA output
in a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin
as RESET/OE, although the opposite polarity is possible on all devices. When
RESET is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the preferred option is active Low RESET, because it can
be driven by the FPGAs INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
When High, this pin disables the internal address counter, puts the DATA output
in a high-impedance state, and forces the device into low-I
CC
standby mode.
GND is the ground connection.
The V
CC
pins are to be connected to the positive voltage supply.
DATA
CLK
2
3
RESET/OE
(OE/RESET)
3
8
CE
GND
V
CC
4
5
7, 8
10
11
18, 20
Pinout Diagrams
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
1
2
3
4
5
6
7
8
9
10
SO20
Top
View
20
19
18
17
16
15
14
13
12
11
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
DS030_04_110102
DATA(D0)
CLK
OE/RESET
CE
1
8
VCC
VCC
NC
GND
DS030_05_060508
2
PD8/PDG8
7
SOG8
3
VO8/VOG8
6
Top View
4
5
DS030 (v1.12) June 20, 2008
Product Specification
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2
R
Product Obsolete
One-Time Programmable Configuration PROMs (XC17S00/XL)
Spartan/XL Family
or Under Obsolescence
If the user-programmable, dual-function D
IN
pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan family takes care of this automatically with an on-
chip default pull-up resistor.
Controlling PROMs
Connecting the Spartan device with the PROM:
•
•
•
The DATA output of the PROM drives the D
IN
input of
the lead Spartan device.
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is driven by the
INIT output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a V
CC
glitch. Other
methods—such as driving RESET/OE from LDC or
system reset—assume that the PROM internal power-
on-reset is always in step with the FPGAs internal
power-on-reset, which is not a safe assumption.
The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC can be
used to drive CE, but must then be unconditionally
High during user operation. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
10 mA maximum.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and
configuration begins with the first program stored in
memory. Since the OE pin is held Low, the address
counters are left unchanged after configuration is complete.
Therefore, to reprogram the FPGA with another program,
the DONE line is pulled Low and configuration begins at the
last value of the address counters.
This method fails if a user applies RESET during the
Spartan device configuration process. The Spartan device
aborts the configuration and then restarts a new
configuration, as intended, but the PROM does not reset its
address counter, since it never saw a High level on its OE
input. The new configuration, therefore, reads the remaining
data in the PROM and interprets it as preamble, length
count etc. Since the Spartan device is the Master, it issues
the necessary number of CCLK pulses, up to 16 million
(2
24
) and DONE goes High. However, the Spartan device
configuration will be completely wrong, with potential
contentions inside the Spartan device and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
•
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The
Spartan FPGA PROM has been designed for compatibility
with the Master Serial mode.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the MODE pin is
Low. Data is read from the PROM sequentially on a single
data line. Synchronization is provided by the rising edge
of the temporary signal CCLK, which is generated during
configuration.
Master Serial mode provides a simple configuration
interface (Figure
1, page 4).
Only a serial data line and two
control lines are required to configure the Spartan device.
Data from the PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming the Spartan Family
PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
DS030 (v1.12) June 20, 2008
Product Specification
www.xilinx.com
3
R
Product Obsolete
One-Time Programmable Configuration PROMs (XC17S00/XL)
Spartan/XL Family
or Under Obsolescence
X-Ref Target - Figure 1
Spartan
Master Serial
MODE
3.3V
V
CC
4.7K
V
CC
V
CC
D
IN
CCLK
DONE
INIT
DATA
CLK
CE
Spartan
PROM
OE/RESET
(Low Resets the Address Pointer)
CCLK
(Output)
D
IN
D
OUT
(Output)
DS030_01_101001
Figure 1:
Master Serial Mode
Note:
The one-time-programmable Spartan PROM supports automatic loading of configuration programs. An early DONE inhibits the
PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.
DS030 (v1.12) June 20, 2008
Product Specification
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4
R
Product Obsolete
One-Time Programmable Configuration PROMs (XC17S00/XL)
Spartan/XL Family
or Under Obsolescence
VCC
GND
X-Ref Target - Figure 2
RESET/
OE
or
OE/
RESET
CE
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
OE
DATA
DS030_02_011300
Figure 2:
Simplified Block Diagram (Does not Show Programming Circuit)
Caution!
Always tie the two V
CC
pins together in the application.
Table 2:
Truth Table for XC17S00 Control Inputs
Control Inputs
RESET
(1)
Inactive
Active
Inactive
Active
Notes:
1.
2.
3.
The XC17S00 RESET input has programmable polarity.
TC = Terminal Count = highest address value. TC + 1 = address 0.
Pull DATA pin to GND or V
CC
to meet I
CCS
standby current.
CE
Low
Low
High
High
Internal Address
(2)
If address < TC: increment
If address > TC: don’t change
Held reset
Not changing
Held reset
Outputs
DATA
Active
High-Z
High-Z
High-Z
(3)
High-Z
(3)
I
CC
Active
Reduced
Active
Standby
Standby
DS030 (v1.12) June 20, 2008
Product Specification
www.xilinx.com
5
