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DS003-3 (v3.2) September 10, 2002
Production Product Specification
Virtex Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:
Advance:
These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary:
These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production:
These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parame-
ters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.
Table 1
correlates the current status of each Virtex device
with a corresponding speed file designation.
Table 1:
Virtex Device Speed Grade Designations
Speed Grade Designations
Device
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
Advance
Preliminary
Production
–6, –5, –4
–6, –5, –4
–6, –5, –4
–6, –5, –4
–6, –5, –4
–6, –5, –4
–6, –5, –4
–6, –5, –4
–6, –5, –4
All specifications are subject to change without notice.
© 1999-2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
1
Virtex™ 2.5 V Field Programmable Gate Arrays
R
Virtex DC Characteristics
Absolute Maximum Ratings
Symbol
V
CCINT
V
CCO
V
REF
V
IN
V
TS
V
CC
T
STG
T
J
Voltage applied to 3-state output
Longest Supply Voltage Rise Time from 1V-2.375V
Storage temperature (ambient)
Junction temperature
(4)
Plastic Packages
Description
(1)
Supply voltage relative to GND
(2)
Supply voltage relative to GND
(2)
Input Reference Voltage
Input voltage relative to GND
(3)
Using V
REF
Internal threshold
–0.5 to 3.0
–0.5 to 4.0
–0.5 to 3.6
–0.5 to 3.6
–0.5 to 5.5
–0.5 to 5.5
50
–65 to +150
+125
Units
V
V
V
V
V
V
ms
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. Power supplies can turn on in any order.
3. For protracted periods (e.g., longer than a day), V
IN
should not exceed V
CCO
by more than 3.6 V.
4. For soldering guidelines and thermal considerations, see the "Device Packaging" infomation on
www.xilinx.com.
Recommended Operating Conditions
Symbol
V
CCINT (1)
Description
Input Supply voltage relative to GND, T
J
= 0
°C
to +85°C
Input Supply voltage relative to GND, T
J
= –40°C to +100°C
Supply voltage relative to GND, T
J
= 0
°C
to +85°C
Supply voltage relative to GND, T
J
= –40°C to +100°C
Input signal transition time
Commercial
Industrial
Commercial
Industrial
Min
2.5 – 5%
2.5 – 5%
1.4
1.4
Max
2.5 + 5%
2.5 + 5%
3.6
3.6
250
Units
V
V
V
V
ns
V
CCO
T
IN
(4)
Notes:
1. Correct operation is guaranteed with a minimum V
CCINT
of 2.375 V (Nominal V
CCINT
–5%). Below the minimum value, all delay
parameters increase by 3% for each 50-mV reduction in V
CCINT
below the specified range.
2. At junction temperatures above those listed as Operating Conditions, delay parameters do increase. Please refer to the TRCE report.
3. Input and output measurement threshold is ~50% of V
CC
.
4. Min and Max values for V
CCO
are I/O Standard dependant.
Module 3 of 4
2
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DS003-3 (v3.2) September 10, 2002
Production Product Specification
R
Virtex™ 2.5 V Field Programmable Gate Arrays
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRIO
I
CCINTQ
Description
Data Retention V
CCINT
Voltage
(below which configuration data can be lost)
Data Retention V
CCO
Voltage
(below which configuration data can be lost)
Quiescent V
CCINT
supply current
(1,3)
Device
All
All
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
I
CCOQ
Quiescent V
CCO
supply current
(1)
XCV50
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
XCV800
XCV1000
I
REF
I
L
C
IN
I
RPU
I
RPD
V
REF
current per V
REF
pin
Input or output leakage current
Input capacitance (sample tested)
BGA, PQ, HQ, packages
Min
2.0
1.2
Max
Units
V
V
50
50
50
75
75
75
100
100
100
2
2
2
2
2
2
2
2
2
20
–10
+10
8
Note (2)
Note (2)
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
pF
mA
mA
All
All
All
All
Pad pull-up (when selected) @ V
in
= 0 V, V
CCO
= 3.3 V (sample
tested)
Pad pull-down (when selected) @ V
in
= 3.6 V (sample tested)
0.25
0.15
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
3. Multiply I
CCINTQ
limit by two for industrial grade.
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
3
Virtex™ 2.5 V Field Programmable Gate Arrays
R
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device
(1)
from 0 V. The current is highest at the fastest suggested ramp rate (0 V to nominal
voltage in 2 ms) and is lowest at the slowest allowed ramp rate (0 V to nominal voltage in 50 ms). For more details on power
supply requirements, see Application Note XAPP158
on
www.xilinx.com.
Product
Virtex Family, Commercial Grade
Virtex Family, Industrial Grade
Description
(2)
Minimum required current supply
Minimum required current supply
Current Requirement
(1,3)
500 mA
2A
Notes:
1. Ramp rate used for this specification is from 0 - 2.7 VDC. Peak current occurs on or near the internal power-on reset threshold of
1.0V and lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents can result if ramp rates are forced to be faster.
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed output currents over the
recommended operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are chosen
to ensure that all standards meet their specifications. The selected standards are tested at minimum V
CCO
for each standard
with the respective V
OL
and V
OH
voltage levels shown. Other standards are sample tested.
Input/Output
Standard
LVTTL
(1)
LVCMOS2
PCI, 3.3 V
PCI, 5.0 V
GTL
GTL+
HSTL I
(3)
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
CTT
AGP
V
IL
V, min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V, max
0.8
.7
44% V
CCINT
0.8
V
REF
– 0.05
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V, min
2.0
1.7
60% V
CCINT
2.0
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
IH
V, max
5.5
5.5
V
CCO
+ 0.5
5.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
OL
V, Max
0.4
0.4
10% V
CCO
0.55
0.4
0.6
0.4
0.4
0.4
V
REF
– 0.6
V
REF
– 0.8
V
REF
– 0.61
V
REF
– 0.80
V
REF
– 0.4
10% V
CCO
V
OH
V, Min
2.4
1.9
90% V
CCO
2.4
n/a
n/a
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
REF
+ 0.6
V
REF
+ 0.8
V
REF
+ 0.61
V
REF
+ 0.80
V
REF
+ 0.4
90% V
CCO
I
OL
mA
24
12
Note 2
Note 2
I
OH
mA
–24
–12
Note 2
Note 2
40
36
8
24
48
8
16
7.6
15.2
8
Note 2
n/a
n/a
–8
–8
–8
–8
–16
–7.6
–15.2
–8
Note 2
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
3. DC input and output levels for HSTL18 (HSTL I/O standard with V
CCO
of 1.8 V) are provided in an HSTL white paper on
www.xilinx.com.
Module 3 of 4
4
www.xilinx.com
1-800-255-7778
DS003-3 (v3.2) September 10, 2002
Production Product Specification
