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Virtex™-E 1.8 V Extended Memory
Field Programmable Gate Arrays
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DS025-3 (v2.3.2) March 14, 2003
Production Product Specification
Virtex-E Extended Memory Electrical Characteristics
Definition of Terms
Electrical and switching characteristics are specified on a
per-speed-grade basis and can be designated as Advance,
Preliminary, or Production. Each designation is defined as
follows:
Advance:
These speed files are based on simulations only
and are typically available soon after device design specifi-
cations are frozen. Although speed grades with this desig-
nation are considered relatively stable and conservative,
some under-reporting might still occur.
Preliminary:
These speed files are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
Production:
These speed files are released once enough
production silicon of a particular device family member has
been characterized to provide full correlation between
speed files and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes. Typ-
ically, the slowest speed grades transition to Production
before faster speed grades.
All specifications are representative of worst-case supply
voltage and junction temperature conditions. The parame-
ters included are common to popular designs and typical
applications. Contact the factory for design considerations
requiring more detailed information.
Table 1
correlates the current status of each Virtex-E
Extended Memory device with a corresponding speed file
designation.
Table 1:
Virtex-E Extended Memory Device
Speed Grade Designations
Speed Grade Designations
Device
XCV405E
XCV812E
Advance
Preliminary
Production
–8, –7, –6
–8, –7, –6
All specifications are subject to change without notice.
DC Characteristics
Absolute Maximum Ratings
Symbol
V
CCINT
V
CCO
V
REF
V
IN (3)
V
TS
V
CC
T
STG
T
J
Description
(1)
Internal Supply voltage relative to GND
Supply voltage relative to GND
Input Reference Voltage
Input voltage relative to GND
Voltage applied to 3-state output
Longest Supply Voltage Rise Time from 0 V – 1.71 V
Storage temperature (ambient)
Junction temperature
(2)
Plastic packages
–0.5 to 2.0
–0.5 to 4.0
–0.5 to 4.0
–0.5 to V
CCO
+0.5
–0.5 to 4.0
50
–65 to +150
+125
Units
V
V
V
V
V
ms
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings can cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time can affect device reliability.
2. For soldering guidelines and thermal considerations, see the device packaging information on
www.xilinx.com.
3. Inputs configured as PCI are fully PCI compliant. This statement takes precedence over any specification that would imply that the
device is not PCI compliant.
© 2000-2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS025-3 (v2.3.2) March 14, 2003
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
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Recommended Operating Conditions
Symbol
V
CCINT
Description
Internal Supply voltage relative to GND, T
J
= 0
°C
to +85°C
Internal Supply voltage relative to GND, T
J
= –40°C to +100°C
V
CCO
Supply voltage relative to GND, T
J
= 0
°C
to +85°C
Supply voltage relative to GND, T
J
= –40°C to +100°C
T
IN
Input signal transition time
Commercial
Industrial
Commercial
Industrial
Min
1.8 – 5%
1.8 – 5%
1.2
1.2
Max
1.8 + 5%
1.8 + 5%
3.6
3.6
250
Units
V
V
V
V
ns
DC Characteristics Over Recommended Operating Conditions
Symbol
V
DRINT
V
DRIO
I
CCINTQ
I
CCOQ
I
L
C
IN
I
RPU
I
RPD
Description
(1)
Data Retention V
CCINT
Voltage
(below which configuration data might be lost)
Data Retention V
CCO
Voltage
(below which configuration data might be lost)
Quiescent V
CCINT
supply current
1
Quiescent V
CCO
supply current
1
Input or output leakage current
Input capacitance (sample tested)
BGA, PQ, HQ, packages
Device
All
All
XCV405E
XCV812E
XCV405E
XCV812E
All
All
All
Note 2
Note 2
–10
Min
1.5
1.2
400
500
2
2
+10
8
0.25
0.25
Max
Units
V
V
mA
mA
mA
mA
µA
pF
mA
mA
Pad pull-up (when selected) @ V
in
= 0 V, V
CCO
= 3.3 V (sample tested)
Pad pull-down (when selected) @ V
in
= 3.6 V (sample tested)
Notes:
1. With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
2. Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device
1
from 0 V. The fastest ramp rate is 0 V to nominal voltage in 2 ms and the slowest allowed
ramp rate is 0 V to nominal voltage in 50 ms. For more details on power supply requirements, see XAPP158
on
www.xilinx.com
.
Product (Commercial Grade)
XCV50E - XCV600E
XCV812E - XCV2000E
XCV2600E - XCV3200E
Virtex-E Family, Industrial Grade
Description
(2)
Minimum required current supply
Minimum required current supply
Minimum required current supply
Minimum required current supply
Current Requirement
(3)
500 mA
1A
1.2 A
2A
Notes:
1. Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.
2. Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
3. Larger currents might result if ramp rates are forced to be faster.
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DS025-3 (v2.3.2) March 14, 2003
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed over the recommended
operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at minimum V
CCO
with the respective V
OL
and
V
OH
voltage levels shown. Other standards are sample tested.
Input/Output
Standard
LVTTL
(1)
LVCMOS2
LVCMOS18
PCI, 3.3 V
GTL
GTL+
HSTL I
(3)
HSTL III
HSTL IV
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
CTT
AGP
V, min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V
IL
V, max
0.8
0.7
20% V
CCO
30% V
CCO
V
REF
– 0.05
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.1
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V
REF
– 0.2
V, min
2.0
1.7
70% V
CCO
50% V
CCO
V
REF
+ 0.05
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.1
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
REF
+ 0.2
V
IH
V, max
3.6
2.7
1.95
V
CCO
+ 0.5
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
3.6
V
OL
V, Max
0.4
0.4
0.4
10% V
CCO
0.4
0.6
0.4
0.4
0.4
V
REF
– 0.6
V
REF
– 0.8
V
REF
– 0.61
V
REF
– 0.80
V
REF
– 0.4
10% V
CCO
V
OH
V, Min
2.4
1.9
V
CCO
– 0.4
90% V
CCO
n/a
n/a
V
CCO
– 0.4
V
CCO
– 0.4
V
CCO
– 0.4
V
REF
+ 0.6
V
REF
+ 0.8
V
REF
+ 0.61
V
REF
+ 0.80
V
REF
+ 0.4
90% V
CCO
I
OL
mA
24
12
8
Note 2
40
36
8
24
48
8
16
7.6
15.2
8
Note 2
I
OH
mA
– 24
– 12
–8
Note 2
n/a
n/a
–8
–8
–8
–8
–16
–7.6
–15.2
–8
Note 2
Notes:
1. V
OL
and V
OH
for lower drive currents are sample tested.
2. Tested according to the relevant specifications.
3. DC input and output levels for HSTL18 (HSTL I/O standard with V
CCO
of 1.8 V) are provided in an HSTL white paper on
www.xilinx.com.
DS025-3 (v2.3.2) March 14, 2003
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1-800-255-7778
Module 3 of 4
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
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LVDS DC Specifications
DC Parameter
Supply Voltage
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
Output Common-Mode Voltage
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
Input Common-Mode Voltage
V
ICM
Differential input voltage =
±350
mV
0.2
1.25
2.2
V
V
OCM
V
IDIFF
R
T
= 100
Ω
across Q and Q signals
Common-mode input voltage = 1.25 V
1.125
100
1.25
350
1.375
NA
V
mV
Symbol
V
CCO
V
OH
V
OL
V
ODIFF
R
T
= 100
Ω
across Q and Q signals
R
T
= 100
Ω
across Q and Q signals
R
T
= 100
Ω
across Q and Q signals
Conditions
Min
2.375
1.25
0.9
250
Typ
2.5
1.425
1.075
350
Max
2.625
1.6
1.25
450
Units
V
V
V
mV
Notes:
1. Refer to the Design Consideration section for termination schematics.
LVPECL DC Specifications
These values are valid at the output of the source termination pack shown under
LVPECL,
with a 100
Ω
differential load only.
The V
OH
levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
ranges. The following table summarizes the DC output specifications of LVPECL.
DC Parameter
V
CCO
V
OH
V
OL
V
IH
V
IL
Differential Input Voltage
Min
3.0
1.8
0.96
1.49
0.86
0.3
Max
Min
3.3
Max
Min
3.6
Max
Units
V
2.11
1.27
2.72
2.125
-
1.92
1.06
1.49
0.86
0.3
2.28
1.43
2.72
2.125
-
2.13
1.30
1.49
0.86
0.3
2.41
1.57
2.72
2.125
-
V
V
V
V
V
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DS025-3 (v2.3.2) March 14, 2003
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Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
Virtex-E Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation net list. All
timing parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
Virtex-E devices unless otherwise noted.
IOB Input Switching Characteristics
Input delays associated with the pad are specified for LVTTL levels. For other standards, adjust the delays with the values
shown in
‘‘IOB Input Switching Characteristics Standard Adjustments’’ on page 6.
Speed Grade
(2)
Description
(1)
Propagation Delays
Symbol
Device
Min
-8
-7
-6
Units
Pad to I output, no delay
Pad to I output, with delay
Pad to output IQ via transparent latch,
no delay
Pad to output IQ via transparent latch,
with delay
Propagation Delays
Clock
T
IOPI
T
IOPID
T
IOPLI
T
IOPLID
All
XCV405E
XCV812E
All
XCV405E
XCV812E
0.43
0.51
0.55
0.75
1.55
1.55
0.8
1.0
1.1
1.4
3.5
3.5
0.8
1.0
1.1
1.5
3.6
3.6
0.8
1.0
1.1
1.6
3.7
3.7
ns, max
ns, max
ns, max
ns, max
ns, max
ns, max
Minimum Pulse Width, High
Minimum Pulse Width, Low
Clock CLK to output IQ
T
CH
T
CL
T
IOCKIQ
All
0.56
0.56
0.18
1.2
1.2
0.4
1.3
1.3
0.7
1.4
1.4
0.7
ns, min
ns, min
ns, max
Setup and Hold Times with respect to Clock at IOB Input Register
Pad, no delay
T
IOPICK
/
T
IOICKP
T
IOPICKD
/
T
IOICKPD
T
IOICECK
/
T
IOCKICE
T
IOSRCKI
All
XCV405E
XCV812E
All
All
0.69 / 0
1.49 / 0
1.49 / 0
0.28 /
0.0
0.38
1.3 / 0
3.4 / 0
3.4 / 0
0.55 /
0.01
0.8
1.4 / 0
3.5 / 0
3.5 / 0
0.7 /
0.01
0.9
1.5 / 0
3.5 / 0
3.5 / 0
0.7 /
0.01
1.0
ns, min
ns, min
ns, min
ns, min
ns, min
Pad, with delay
ICE input
SR input (IFF, synchronous)
Set/Reset Delays
SR input to IQ (asynchronous)
GSR to output IQ
T
IOSRIQ
T
GSRQ
All
All
0.54
3.88
1.1
7.6
1.2
8.5
1.4
9.7
ns, max
ns, max
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
2. Input timing i for LVTTL is measured at 1.4 V. For other I/O standards, see
Table 3.
DS025-3 (v2.3.2) March 14, 2003
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1-800-255-7778
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