UltraScale Architecture and
Product Data Sheet: Overview
DS890 (v3.6) November 12, 2018
Product Specification
General Description
Xilinx® UltraScale™ architecture comprises high-performance FPGA, MPSoC, and RFSoC families that address a vast spectrum of
system requirements with a focus on lowering total power consumption through numerous innovative technological
advancements.
Kintex® UltraScale FPGAs:
High-performance FPGAs with a focus on price/performance, using both monolithic and
next-generation stacked silicon interconnect (SSI) technology. High DSP and block RAM-to-logic ratios and next-generation
transceivers, combined with low-cost packaging, enable an optimum blend of capability and cost.
Kintex UltraScale+™ FPGAs:
Increased performance and on-chip UltraRAM memory to reduce BOM cost. The ideal mix of
high-performance peripherals and cost-effective system implementation. Kintex UltraScale+ FPGAs have numerous power
options that deliver the optimal balance between the required system performance and the smallest power envelope.
Virtex® UltraScale FPGAs:
High-capacity, high-performance FPGAs enabled using both monolithic and next-generation SSI
technology. Virtex UltraScale devices achieve the highest system capacity, bandwidth, and performance to address key market and
application requirements through integration of various system-level functions.
Virtex UltraScale+ FPGAs:
The highest transceiver bandwidth, highest DSP count, and highest on-chip and in-package memory
available in the UltraScale architecture. Virtex UltraScale+ FPGAs also provide numerous power options that deliver the optimal
balance between the required system performance and the smallest power envelope.
Zynq® UltraScale+ MPSoCs:
Combine the Arm® v8-based Cortex®-A53 high-performance energy-efficient 64-bit application
processor with the Arm Cortex-R5 real-time processor and the UltraScale architecture to create the industry's first All
Programmable MPSoCs. Provide unprecedented power savings, heterogeneous processing, and programmable acceleration.
Zynq® UltraScale+ RFSoCs:
Combine RF data converter subsystem and forward error correction with industry-leading
programmable logic and heterogeneous processing capability. Integrated RF-ADCs, RF-DACs, and soft-decision FECs (SD-FEC)
provide the key subsystems for multiband, multi-mode cellular radios and cable infrastructure.
Family Comparisons
Table 1:
Device Resources
Kintex
UltraScale
FPGA
MPSoC Processing System
RF-ADC/DAC
SD-FEC
System Logic Cells (K)
Block Memory (Mb)
UltraRAM (Mb)
HBM DRAM (GB)
DSP (Slices)
DSP Performance (GMAC/s)
Transceivers
Max. Transceiver Speed (Gb/s)
Max. Serial Bandwidth (full duplex) (Gb/s)
Memory Interface Performance (Mb/s)
I/O Pins
768–5,520
8,180
12–64
16.3
2,086
2,400
312–832
1,368–3,528
6,287
16–76
32.75
3,268
2,666
280–668
600–2,880
4,268
36–120
30.5
5,616
2,400
338–1,456
318–1,451
12.7–75.9
356–1,143
12.7–34.6
0–36
783–5,541
44.3–132.9
862–3,780
23.6–94.5
90–360
0–8
2,280–12,288
21,897
32–128
58.0
8,384
2,666
208–832
240–3,528
6,287
0–72
32.75
3,268
2,666
82–668
3,145–4,272
7,613
8–16
32.75
1,048
2,666
280–408
103–1,143
4.5–34.6
0–36
Kintex
UltraScale+
FPGA
Virtex
UltraScale
FPGA
Virtex
UltraScale+
FPGA
Zynq
UltraScale+
MPSoC
✓
Zynq
UltraScale+
RFSoC
✓
✓
✓
678–930
27.8–38.0
13.5–22.5
© Copyright 2013–2018 Xilinx, Inc. Xilinx, the Xilinx logo, Alveo, Artix, ISE, Kintex, Spartan, Versal, Virtex, Vivado, Zynq, and other designated brands included herein are
trademarks of Xilinx in the United States and other countries. AMBA, AMBA Designer, Arm, Arm1176JZ-S, CoreSight, Cortex, and PrimeCell are trademarks of Arm in the
EU and other countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS890 (v3.6) November 12, 2018
Product Specification
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UltraScale Architecture and Product Data Sheet: Overview
Summary of Features
RF Data Converter Subsystem Overview
Most Zynq UltraScale+ RFSoCs include an RF data converter subsystem, which contains multiple radio
frequency analog to digital converters (RF-ADCs) and multiple radio frequency digital to analog
converters (RF-DACs). The high-precision, high-speed, power efficient RF-ADCs and RF-DACs can be
individually configured for real data or can be configured in pairs for real and imaginary I/Q data. The
12-bit RF-ADCs support sample rates up to 2.058GSPS or 4.096GSPS, depending on the selected device.
The 14-bit RF-DACs support sample rates up to 6.554GSPS.
Soft Decision Forward Error Correction (SD-FEC) Overview
Some Zynq UltraScale+ RFSoCs include highly flexible soft-decision FEC blocks for decoding and encoding
data as a means to control errors in data transmission over unreliable or noisy communication channels.
The SD-FEC blocks support low-density parity check (LDPC) decode/encode and Turbo decode for use in
5G wireless, backhaul, DOCSIS, and LTE applications.
Processing System Overview
Zynq UltraScale+ MPSoCs and RFSoCs feature dual and quad core variants of the Arm Cortex-A53 (APU)
with dual-core Arm Cortex-R5 (RPU) processing system (PS). Some devices also include a dedicated Arm
Mali™-400 MP2 graphics processing unit (GPU). See
Table 2.
Table 2:
Zynq UltraScale+ MPSoC and RFSoC Device Features
MPSoC
CG Devices
EG Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5
Mali-400MP2
–
EV Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5
Mali-400MP2
H.264/H.265
RFSoC
DR Devices
Quad-core Arm Cortex-A53
Dual-core Arm Cortex-R5
–
–
APU
RPU
GPU
VCU
Dual-core Arm Cortex-A53
Dual-core Arm Cortex-R5
–
–
To support the processors' functionality, a number of peripherals with dedicated functions are included in
the PS. For interfacing to external memories for data or configuration storage, the PS includes a
multi-protocol dynamic memory controller, a DMA controller, a NAND controller, an SD/eMMC controller
and a Quad SPI controller. In addition to interfacing to external memories, the APU also includes a Level-1
(L1) and Level-2 (L2) cache hierarchy; the RPU includes an L1 cache and Tightly Coupled memory
subsystem. Each has access to a 256KB on-chip memory.
For high-speed interfacing, the PS includes 4 channels of transmit (TX) and receive (RX) pairs of
transceivers, called PS-GTR transceivers, supporting data rates of up to 6.0Gb/s. These transceivers can
interface to the high-speed peripheral blocks that support PCIe at 5.0GT/s (Gen2) as a root complex or
Endpoint in x1, x2, or x4 configurations; Serial-ATA (SATA) at 1.5Gb/s, 3.0Gb/s, or 6.0Gb/s data rates; and
up to two lanes of Display Port at 1.62Gb/s, 2.7Gb/s, or 5.4Gb/s data rates. The PS-GTR transceivers can
also interface to components over USB 3.0 and Serial Gigabit Media Independent Interface (SGMII).
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UltraScale Architecture and Product Data Sheet: Overview
For general connectivity, the PS includes: a pair of USB 2.0 controllers, which can be configured as host,
device, or On-The-Go (OTG); an I2C controller; a UART; and a CAN2.0B controller that conforms to
ISO11898-1. There are also four triple speed Ethernet MACs and 128 bits of GPIO, of which 78 bits are
available through the MIO and 96 through the EMIO.
High-bandwidth connectivity based on the Arm AMBA® AXI4 protocol connects the processing units with
the peripherals and provides interface between the PS and the programmable logic (PL).
For additional information, go to:
DS891,
Zynq UltraScale+ MPSoC Overview.
I/O, Transceiver, PCIe, 100G Ethernet, and 150G Interlaken
Data is transported on and off chip through a combination of the high-performance parallel SelectIO™
interface and high-speed serial transceiver connectivity. I/O blocks provide support for cutting-edge
memory interface and network protocols through flexible I/O standard and voltage support. The serial
transceivers in the UltraScale architecture-based devices transfer data up to 58.0Gb/s, enabling 25G+
backplane designs with dramatically lower power per bit than previous generation transceivers. All
transceivers, except the PS-GTR, support the required data rates for 8.0GT/s (Gen3) and 16.0GT/s (Gen4)
for PCIe. The integrated blocks for PCIe can be configured as either Endpoint or Root Port, supporting a
variety of link widths and speeds depending on the targeted device speed grade and package. Integrated
blocks for 150Gb/s Interlaken and 100Gb/s Ethernet (100G MAC/PCS) extend the capabilities of UltraScale
devices, enabling simple, reliable support for Nx100G switch and bridge applications. Virtex UltraScale+
HBM devices include Cache Coherent Interconnect for Accelerators (CCIX) ports for coherently sharing data
with different processors.
Clocks and Memory Interfaces
UltraScale devices contain powerful clock management circuitry, including clock synthesis, buffering, and
routing components that together provide a highly capable framework to meet design requirements. The
clock network allows for extremely flexible distribution of clocks to minimize the skew, power
consumption, and delay associated with clock signals. The clock management technology is tightly
integrated with dedicated memory interface circuitry to enable support for high-performance external
memories, including DDR4. In addition to parallel memory interfaces, UltraScale devices support serial
memories, such as hybrid memory cube (HMC).
Routing, SSI, Logic, Storage, and Signal Processing
Configurable Logic Blocks (CLBs) containing 6-input look-up tables (LUTs) and flip-flops, DSP slices with
27x18 multipliers, 36Kb block RAMs with built-in FIFO and ECC support, and 4Kx72 UltraRAM blocks (in
UltraScale+ devices) are all connected with an abundance of high-performance, low-latency interconnect.
In addition to logical functions, the CLB provides shift register, multiplexer, and carry logic functionality as
well as the ability to configure the LUTs as distributed memory to complement the highly capable and
configurable block RAMs. The DSP slice, with its 96-bit-wide XOR functionality, 27-bit pre-adder, and
30-bit A input, performs numerous independent functions including multiply accumulate, multiply add,
and pattern detect. In addition to the device interconnect, in devices using SSI technology, signals can
cross between super-logic regions (SLRs) using dedicated, low-latency interface tiles. These combined
routing resources enable easy support for next-generation bus data widths. Virtex UltraScale+ HBM
devices include up to 8GB of high bandwidth memory.
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UltraScale Architecture and Product Data Sheet: Overview
Configuration, Encryption, and System Monitoring
The configuration and encryption block performs numerous device-level functions critical to the
successful operation of the FPGA, MPSoC, or RFSoC. This high-performance configuration block enables
device configuration from external media through various protocols, including PCIe, often with no
requirement to use multi-function I/O pins during configuration. The configuration block also provides
256-bit AES-GCM decryption capability at the same performance as unencrypted configuration.
Additional features include SEU detection and correction, partial reconfiguration support, and
battery-backed RAM or eFUSE technology for AES key storage to provide additional security. The System
Monitor enables the monitoring of the physical environment via on-chip temperature and supply sensors
and can also monitor up to 17 external analog inputs. With Zynq UltraScale+ MPSoCs and RFSoCs, the
device is booted via the Configuration and Security Unit (CSU), which supports secure boot via the 256-bit
AES-GCM and SHA/384 blocks. The cryptographic engines in the CSU can be used after boot for user
encryption.
Migrating Devices
UltraScale and UltraScale+ families provide footprint compatibility to enable users to migrate designs
from one device or family to another. Any two packages with the same footprint identifier code are
footprint compatible. For example, Kintex UltraScale devices in the A1156 packages are footprint
compatible with Kintex UltraScale+ devices in the A1156 packages. Likewise, Virtex UltraScale devices in
the B2104 packages are compatible with Virtex UltraScale+ devices and Kintex UltraScale devices in the
B2104 packages. All valid device/package combinations are provided in the Device-Package Combinations
and Maximum I/Os tables in this document. Refer to
UG583,
UltraScale Architecture PCB Design User Guide
for more detail on migrating between UltraScale and UltraScale+ devices and packages.
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UltraScale Architecture and Product Data Sheet: Overview
Kintex UltraScale FPGA Feature Summary
Table 3:
Kintex UltraScale FPGA Feature Summary
KU025
(1)
System Logic Cells
CLB Flip-Flops
CLB LUTs
Maximum Distributed RAM (Mb)
Block RAM Blocks
Block RAM (Mb)
CMTs (1 MMCM, 2 PLLs)
I/O DLLs
Maximum HP I/Os
(2)
Maximum HR I/Os
(3)
DSP Slices
System Monitor
PCIe Gen3 x8
150G Interlaken
100G Ethernet
GTH 16.3Gb/s Transceivers
(4)
GTY 16.3Gb/s Transceivers
(5)
Transceiver Fractional PLLs
318,150
290,880
145,440
4.1
360
12.7
6
24
208
104
1,152
1
1
0
0
12
0
0
KU035
444,343
406,256
203,128
5.9
540
19.0
10
40
416
104
1,700
1
2
0
0
16
0
0
KU040
530,250
484,800
242,400
7.0
600
21.1
10
40
416
104
1,920
1
3
0
0
20
0
0
KU060
725,550
663,360
331,680
9.1
1,080
38.0
12
48
520
104
2,760
1
3
0
0
32
0
0
KU085
1,088,325
995,040
497,520
13.4
1,620
56.9
22
56
572
104
4,100
2
4
0
0
56
0
0
KU095
1,176,000
1,075,200
537,600
4.7
1,680
59.1
16
64
650
52
768
1
4
2
2
32
32
16
KU115
1,451,100
1,326,720
663,360
18.3
2,160
75.9
24
64
676
156
5,520
2
6
0
0
64
0
0
Notes:
1.
2.
3.
4.
5.
Certain advanced configuration features are not supported in the KU025. Refer to the
Configuring FPGAs
section for details.
HP = High-performance I/O with support for I/O voltage from 1.0V to 1.8V.
HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.
GTH transceivers in SF/FB packages support data rates up to 12.5Gb/s. See
Table 4.
GTY transceivers in Kintex UltraScale devices support data rates up to 16.3Gb/s. See
Table 4.
DS890 (v3.6) November 12, 2018
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