This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for the MPC823.
Note:
Visit our website at www.motorola.com if you are using a frequency other than
25, 40, or 50MHz. Our website contains a spreadsheet that you can use to
calculate the timing for your specific system frequency.
This device contains circuitry protecting against damage from high-static voltage or electrical
fields. However, it is advised that precautions be taken to avoid application of any voltages
higher than the maximum-rated voltages to this high-impedance circuit. Reliability of operation
is enhanced if unused inputs are tied to an appropriate logic voltage level (either GND or V
CC
).
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. PowerPC
is a registered trademark of IBM Corp. and is used by Motorola under license from IBM Corp. I
2
C is a registered trademark of Philips Corporation.
Ó
2000 Motorola, Inc.All Rights Reserved.
MAXIMUM RATINGS (GND = 0V)
RATING
Supply Voltage
SYMBOL
VDDH
VDD
KAPWR
VDDSYN
Input Voltage (JTAG and GPIO)
Input Voltage (All other pins)
Operating Temperature
VIN
VIN
T
A
VALUE
-0.3 to 4.0
-0.3 to 4.0
-0.3 to 4.0
-0.3 to 4.0
-0.3 to 5.8
-0.3 to 3.3
0 to 70û
or
-40û to 85û
-55 to +150
UNIT
V
V
V
V
V
V
ûC
Storage Temperature Range
NOTES:
1.
T
STG
ûC
Functional operating conditions are given in
DC Electrical Characteristics (VCC = 3.0 - 3.6
V)
. Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond those listed may affect device reliability or cause
permanent damage to the device.
CAUTION
: The JTAG and GPIO input voltages cannot be more than 2.5 V greater than
supply voltage, this restriction applies also on Òpower-onÓ as well as on normal operation.
5 Volt friendly inputs are inputs that tolerate 5 volts for JTAG and GPIO pins.
If you are using Mask Revision Base #F98S (Revision 0), all pins except EXTAL and CLK4IN
are 5V tolerant inputs.
2.
3.
4.
THERMAL CHARACTERISTICS
CHARACTERISTIC
Thermal Resistance for BGA
SYMBOL
q
Jc
VALUE
~30
UNIT
°
C/W
2
MPC823 ELECTRICAL SPECIFICATIONS
MOTOROLA
POWER CONSIDERATIONS
The average chip-junction temperature
,
T
J
,
in
°
C can be obtained from
T
J
= T
A
+ (P
D
¥
q
JA
)
where
T
A
=
q
JA
=
P
D
=
P
INT
=
P
I/O
=
Ambient Temperature
,
¥
C
Package Thermal Resistance
,
Junction to Ambient
,
¥
C/W
P
INT
+ P
I/O
I
DD
x V
DD
,
WattsÑChip Internal Power
Power Dissipation on Input and Output PinsÑUser Determined
(1)
For most applications P
I/O
< 0.3
¥
P
INT
and can be neglected. If P
I/O
is neglected
,
an approximate
relationship between P
D
and T
J
is:
P
D
=
K
Õ
(T
J
+ 273
¥
C)
(2)
Solving equations (1) and (2) for K gives
K=
P
D
¥
(T
A
+ 273
¥
C) + q
JA
¥ P
D
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring P
D
(at equilibrium) for a known T
A
. Using this value of K
,
the values of P
D
and T
J
can be obtained by solving equations (1) and (2) iteratively for any value of T
A
.
Layout Practices
Each V
CC
pin on the MPC823 should be provided with a low-impedance path to the boardÕs
supply. Each GND pin should be provided with a low-impedance path to ground. The power
supply pins drive distinct groups of logic on chip. The V
CC
power supply should be bypassed to
ground using at least four 0.1
m
F bypass capacitors located as close as possible to the four
sides of the package. The capacitor leads and associated printed circuit traces connecting to
chip V
CC
and GND should be kept to less than half an inch per capacitor lead. A four-layer
board that employs two inner layers as V
CC
and GND planes should be used.
All output pins on the MPC823 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections
caused by these fast output switching times. This recommendation particularly applies to the
address and data busses. Maximum PC trace lengths of six inches are recommended.
Capacitance calculations should consider all device loads as well as parasitic capacitances
due to the PC traces. Attention to proper PCB layout and bypassing becomes especially critical
in systems with higher capacitive loads because these loads create higher transient currents
in the V
CC
and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins.
