Advance Information
MPC8260AEC/D
Rev. 0.5 3/2002
MPC826xA (HiP4) Family
Hardware Specifications
This document contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications for HiP4-enhanced derivatives of the
PowerQUICC II™ MPC8260 communications processor (collectively referred to as the
MPC826xA).
The following topics are addressed:
Topic
Section 1.1, “Features”
Section 1.2, “Electrical and Thermal Characteristics”
Section 1.2.1, “DC Electrical Characteristics”
Section 1.2.2, “Thermal Characteristics”
Section 1.2.3, “Power Considerations”
Section 1.2.4, “AC Electrical Characteristics”
Section 1.3, “Clock Configuration Modes”
Section 1.3.1, “Local Bus Mode”
Section 1.3.2, “PCI Mode”
Section 1.4, “Pinout”
Section 1.5, “Package Description”
Section 1.6, “Ordering Information”
Page
3
8
8
12
12
13
19
19
22
28
41
43
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 1 shows the functionality that defines each derivative of the HiP4-enhanced PowerQUICC II family.
Table 1. HiP4 PowerQUICC II Family Derivatives
Derivatives
Functionality
MPC8260A MPC8264A MPC8265A MPC8266A
HiP4 Process Enhancements
PCI Bridge
Transmission Convergence (TC) Layer
Inverse Multiplexing for ATM (IMA)
X
X
X
X
X
X
X
X
X
X
Until a revision of the current
MPC8260 PowerQUICC II User’s Manual
(Rev 0) is available, several
addendum documents supply information about the functionality of HiP4-enhanced PowerQUICC II
devices. Table 2 lists each device and its related documentation.
Table 2. HiP4 PowerQUICC II Documentation
Derivatives
Document
MPC8260A MPC8264A MPC8265A MPC8266A
MPC8260 PowerQUICC II User’s Manual
, Rev 0
(order number: MPC8260UM/D)
MPC8260A (HiP4) Supplement to the MPC8260
PowerQUICC II User’s Manual
(Preliminary)
(order number: MPC8260AUM/D)
PCI Bridge Functional Specification (Preliminary)
(order number: MPC8265AUMAD/D)
TC Layer Functional Specification (Preliminary)
(order number: MPC8264AUMAD/D)
IMA Functional Specification (Preliminary)
(order number: MPC8266AUMAD/D)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
Figure 1 shows the block diagram for the HiP4 superset device, the MPC8266A.
16 Kbytes
I-Cache
I-MMU
G2 Core
System Interface Unit
(SIU)
16 Kbytes
D-Cache
D-MMU
Bus Interface Unit
60x-to-PCI
Bridge
2,3
60x-to-Local
Bridge
Memory Controller
Timers
Parallel I/O
Baud Rate
Generators
32-bit RISC Microcontroller
and Program ROM
IMA
1,3
Microcode
60x Bus
PCI Bus
2,3
32 bits, up to 66 MHz
or
Local Bus
32 bits, up to 83 MHz
Communication Processor Module (CPM)
Interrupt
Controller
32 Kbytes
Dual-Port RAM
Serial
DMAs
4 Virtual
IDMAs
Clock Counter
System Functions
MCC1
MCC2
FCC1
FCC2
FCC3
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
I
2
C
TC Layer Hardware
1,3
Time Slot Assigner
Serial Interface
8 TDM Ports
3 MII
Ports
2 UTOPIA
Ports
Non-Multiplexed
I/O
Notes:
1. MPC8264A
2. MPC8265A
3. MPC8266A
Figure 1. MPC8266A Block Diagram
1.1
•
Features
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 133–300 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
Separate power supply for internal logic (1.8 V) and for I/O (3.3V)
The major features of the MPC826xA family are as follows:
•
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
Features
•
•
•
•
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge (MPC8265A and MPC8266A only)
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
•
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
•
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
— Dedicated interface logic for SDRAM
•
•
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible
support for communications protocols
4
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MOTOROLA
Features
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5,
AAL1, AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external
connections
– Transparent
– HDLC—Up to T3 rates (clear channel)
— Two multichannel controllers (MCCs)
– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split
into four subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One inter-integrated circuit (I
2
C) controller (identical to the MPC860 I
2
C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to eight TDM interfaces
– Supports two groups of four TDM channels for a total of eight TDMs
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
MOTOROLA
MPC826xA (HiP4) Family Hardware Specifications
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
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