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QPRO XQ4000XL Series QML
High-Reliability FPGAs
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DS029 (v1.3) June 25, 2000
Product Specification
•
Development system runs on most common computer
platforms
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
Highest capacity—over 180,000 usable gates
Additional routing over XQ4000E
- Almost twice the routing capacity for high-density
designs
Buffered Interconnect for maximum speed
New latch capability in configurable logic blocks
Improved VersaRing™ I/O interconnect for better Fixed
pinout flexibility
- Virtually unlimited number of clock signals
Optional multiplexer or 2-input function generator on
device outputs
5V tolerant I/Os
0.35
µm
SRAM process
XQ4000X Series Features
•
•
•
Certified to MIL-PRF-38535 Appendix A QML
(Qualified Manufacturer Listing)
Ceramic and plastic packages
Also available under the following standard microcircuit
drawings (SMD)
- XQ4013XL 5962-98513
- XQ4036XL 5962-98510
- XQ4062XL 5962-98511
- XQ4085XL 5962-99575
For more information contact the Defense Supply
Center Columbus (DSCC)
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
Available in -3 speed
System featured Field-Programmable Gate Arrays
- SelectRAM™ memory: on-chip ultra-fast RAM with
·
synchronous write option
·
dual-port RAM option
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
- Internal 3-state bus capability
- Eight global low-skew clock or signal distribution
networks
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•
•
•
•
•
•
•
•
•
•
Introduction
The QPRO™ XQ4000XL Series high-performance,
high-capacity Field Programmable Gate Arrays (FPGAs)
provide the benefits of custom CMOS VLSI, while avoiding
the initial cost, long development cycle, and inherent risk of
a conventional masked gate array.
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
Refer to the complete Commercial XC4000XL Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
•
•
•
•
System performance beyond 50 MHz
Flexible array architecture
Low power segmented routing architecture
Systems-oriented features
- IEEE 1149.1-compatible boundary scan logic
support
•
•
- Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12 mA sink current per XQ4000XL output
Configured by loading binary file
- Unlimited reprogrammability
Readback capability
- Program verification
- Internal node observability
© 2000 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
1
QPRO XQ4000XL Series QML High-Reliability FPGAs
R
Table 1:
XQ4000XL Series High Reliability Field Progammable Gate Arrays
Max
Logic
Gates
(No
RAM)
(1)
13,000
36,000
62,000
85,000
Max.
RAM
Bits (No
Logic)
18,432
41,472
73,728
100,352
Typical Gate
Range
(Logic and
RAM)
(1)
10,000-30,000
22,000-65,000
40,000-130,000
55,000-180,000
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
Logic
Cells
2432
3078
5472
7448
CLB
Matrix
24x24
36x36
48x48
56x56
Total
CLBs
576
1,296
2,304
3,136
Number
of
Flip-Flops
1,536
3,168
5,376
7,168
Max.
User
I/O
192
288
384
448
Packages
PG223, CB228,
PQ240, BG256
PG411, CB228,
HQ240, BG352
PG475, CB228,
HQ240, BG432
PG475, CB228,
HQ240, BG432
Notes:
1. Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM.
2
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DS029 (v1.3) June 25, 2000
Product Specification
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QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Preliminary:
Unmarked:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or
devicefamilies. Values are subject to change. Use as estimates, not for production.
Based on preliminary characterization. Further changes are not expected.
Specifications not identified as either Advance or Preliminary are to be considered Final.
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c.
parameter delay specifications included in this document
are derived from measuring internal test patterns. All speci-
fications are representative of worst-case supply voltage
and junction temperature conditions. The parameters
included are common to popular designs and typical appli-
cations. For design considerations requiring more detailed
timing information, see the appropriate family AC supple-
ments available on the Xilinx web site at:
http://www.xilinx.com/partinfo/databook.htm.
Absolute Maximum Ratings
(1)
Symbol
V
CC
V
IN
V
TS
V
CCt
T
STG
T
SOL
T
J
Supply voltage relative to GND
Input voltage relative to GND
(2)
Voltage applied to High-Z output
(2)
Longest supply voltage rise time from 1V to 3V
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)
Junction temperature
Ceramic package
Plastic package
Description
–0.5 to 4.0
–0.5 to 5.5
–0.5 to 5.5
50
–65 to +150
+260
+150
+125
Units
V
V
V
ms
°C
°C
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2. Maximum DC overshoot or undershoot above V
CC
or below GND must be limited to either 0.5V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to –2.0 V or overshoot to V
CC
+ 2.0V, provided this over- or undershoot
lasts less than 10 ns and with the forcing current being limited to 200 mA.
Recommended Operating Conditions
(1)
Symbol
V
CC
V
IH
V
IL
T
IN
Description
Supply voltage relative to GND, T
J
= –55°C to +125°C
Supply voltage relative to GND, T
C
= –55°C to +125°C
High-level input voltage
(2)
Low-level input voltage
Input signal transition time
Plastic
Ceramic
Min
3.0
3.0
50% of V
CC
0
-
Max
3.6
3.6
5.5
30% of V
CC
250
Units
V
V
V
V
ns
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Input and output measurement threshold is ~50% of V
CC
.
DS029 (v1.3) June 25, 2000
Product Specification
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1-800-255-7778
3
QPRO XQ4000XL Series QML High-Reliability FPGAs
R
XQ4000XL DC Characteristics Over Recommended Operating Conditions
Symbol
V
OH
V
OL
V
DR
I
CCO
I
L
C
IN
I
RPU
I
RPD
I
RLL
Description
High-level output voltage at I
OH
= –4 mA, V
CC
min (LVTTL)
High-level output voltage at I
OH
= –500
µA,
(LVCMOS)
Low-level output voltage at I
OL
= 12 mA, V
CC
min (LVTTL)
(1)
Low-level output voltage at I
OL
= 1500
µA,
(LVCMOS)
Data retention supply voltage (below which configuration data may be lost)
Quiescent FPGA supply current
(2)
Input or output leakage current
Input capacitance (sample tested)
BGA, PQ, HQ, packages
PGA packages
Pad pull-up (when selected) at V
IN
= 0V (sample tested)
Pad pull-down (when selected) at V
IN
= 3.6V (sample tested)
Horizontal longline pull-up (when selected) at logic Low
Min
2.4
90% V
CC
-
-
2.5
-
–10
-
-
0.02
0.02
0.3
Max
-
-
0.4
10% V
CC
-
5
+10
10
16
0.25
0.15
2.0
Units
V
V
V
V
V
mA
µA
pF
pF
mA
mA
mA
Notes:
1. With up to 64 pins simultaneously sinking 12 mA.
2. With no output current loads, no active input or Longline pull-up resistors, all I/O pins in a High-Z state and floating.
Power-On Power Supply Requirements
Xilinx FPGAs require a minimum rated power supply current
capacity to insure proper initialization, and the power supply
ramp-up time does affect the current required. A fast
ramp-up time requires more current than a slow ramp-up
time. The slowest ramp-up time is 50 ms. Current capacity
is not specified for a ramp-up time faster than 2 ms. The cur-
rent capacity varies linealy with ramp-up time,
e.g.,
an
XQ4036XL with a ramp-up time of 25 ms would require a
capacity predicted by the point on the straight line drawn
from 1A at 120
µs
to 500 mA at 50 ms at the 25 ms time
mark. This point is approximately 750 mA
.
Ramp-up Time
Product
XQ4013 - 36XL
XC4062XL
XC4085XL
(1)
Description
Minimum required current supply
Minimum required current supply
Minimum required current supply
Fast (120
µs)
1A
2A
2A
(1)
Slow (50 ms)
500 mA
500 mA
500 mA
Notes:
1. The XC4085XL fast ramp-up time is 5 ms.
2. Devices are guaranteed to initialize properly with the minimum current listed above. A larger capacity power supply may result in a
larger initialization current.
3. This specification applies to Commercial and Industrial grade products only.
4. Ramp-up Time is measured from 0V
DC
to 3.6V
DC
. Peak current required lasts less than 3 ms, and occurs near the internal power
on reset threshold voltage. After initialization and before configuration, I
CC
max is less than 10 mA.
4
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DS029 (v1.3) June 25, 2000
Product Specification
R
QPRO XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL AC Switching Characteristic
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by
the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature)
Global Buffer Switching Characteristics
All
Min
0.6
1.1
1.4
1.6
-3
Max
3.6
4.8
6.3
-
-1
Max
-
-
-
5.7
Units
ns
ns
ns
ns
Symbol
T
GLS
Description
Delay from pad through Global Low Skew buffer, to any
clock K
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
Global Early BUFGEs 1, 2, 5, and 6 to IOB Clock Characteristics
All
Min
0.4
0.3
0.3
0.4
-3
Max
2.4
3.1
4.9
-
-1
Max
-
-
-
4.7
Units
ns
ns
ns
ns
Symbol
T
GE
Description
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 1, 2, 5 and 6.
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
Global Early BUFGEs 3, 4, 7, and 8 to IOB Clock Characteristics
All
Min
0.7
0.9
1.2
1.3
-3
Max
2.4
4.7
5.9
-
-1
Max
-
-
-
5.5
Units
ns
ns
ns
ns
Symbol
T
GE
Description
Delay from pad through Global Early buffer, to any IOB
clock. Values are for BUFGEs 3, 4, 7 and 8.
Device
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
5
