XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
APRIL 2013
REV. 3.1.0
GENERAL DESCRIPTION
The XR16C854/854D
1
(854) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 128 bytes of transmit and receive
FIFOs, transmit and receive FIFO counters and
trigger levels, automatic hardware and software flow
control, and data rates of up to 2 Mbps.
Each UART has a set of registers that provide the
user with operating status and control, receiver error
indications, and modem serial interface controls.
System interrupts may be tailored to meet design
requirements. An internal loopback capability allows
onboard diagnostics.
The 854 is available in 64-pin LQFP, 68-pin PLCC
and 100-pin QFP packages. The 64-pin package
only offers the 16 mode interface, but the 68 and 100
pin packages offer an additional 68 mode interface
which allows easy integration with Motorola
processors.
The XR16C854CV (64 pin) offers three state interrupt
outputs while the XR16C854DV provides continuous
interrupt outputs. The 100 pin package provides
additional FIFO status outputs (TXRDY# and
RXRDY# A-D), separate infrared transmit data
outputs (IRTX A-D) and channel C external clock
input (CHCCLK). The XR16C854/854D is compatible
with the industry standard ST16C554/554D and
ST16C654/654D.
N
OTE
:
1 Covered by U.S. Patent #5,649,122 and #5,949,787.
FEATURES
Added feature in devices with top mark date code of
"F2 YYWW" and newer:
s
5 volt tolerant inputs
•
2.97 to 5.5 Volt Operation
•
Pin-to-pin compatible with the industry standard
ST16C554 and ST16C654 and TI’s TL16C554N
and TL16C754BFN
•
Intel or Motorola Data Bus Interface select
•
Four independent UART channels
s
s
s
s
s
s
s
s
s
Register Set Compatible to 16C550
Data rates of up to 2 Mbps
Transmit and Receive FIFOs of 128 bytes
Programmable TX and RX FIFO Trigger Levels
Transmit and Receive FIFO Level Counters
Automatic Hardware (RTS/CTS) Flow Control
Selectable Auto RTS Flow Control Hysteresis
Automatic Software (Xon/Xoff) Flow Control
Wireless Infrared (IrDA 1.0) Encoder/Decoder
•
Sleep Mode (200 uA typical)
•
Crystal oscillator or external clock input
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Control
F
IGURE
1. XR16C854 B
LOCK
D
IAGRAM
A2:A0
D7:D0
IOR#
IOW #
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
Data Bus
Interface
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
UART Channel A
UART 128 Byte TX FIFO
Regs
BRG
IR
TX & RX
ENDEC
128 Byte RX FIFO
2.97V to 5.5V VCC
GND
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#, OP2A#
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#, OP2B#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#, OP2C#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#, OP2D#
XTAL1
XTAL2
Crystal O sc/Buffer
854 BLK
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
D4
D5
D6
D7
RXD
VCC
CDD#
RID#
RIA#
TXRDYD#
RXRDYD#
INTSEL
CDA#
RXRDYA#
GND
CDD#
GND
RXA
VCC
RXD
RID#
GND
RXA
D7
D6
D5
D4
D3
D2
D1
D0
D3
D2
D1
D0
RIA#
CDA#
RXRDYA#
RXRDYD#
TXRDYD#
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
99
93
92
88
90
87
89
83
86
91
85
84
82
81
98
97
96
95
94
100
100
N.C.
80
N.C.
1
N.C.
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
24
IRTXB
TXRDYB#
N.C.
N.C.
N.C.
N.C.
N.C.
25
26
27
28
29
30
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
FSRS#
IRTXD
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
IRTXC
TXRDYC#
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
TXRDYA#
IRTXA
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
3
2
1
XR16C854/854D
N.C.
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
N.C.
N.C.
N.C.
N.C.
N.C.
TXRDYC#
IRTXC
DSRC#
CTSC#
DTRC#
VCC
RTSC#
N.C.
A4
TXC
N.C.
TXD
N.C.
N.C.
RTSD#
GND
DTRD#
CTSD#
DSRD#
IRTXD
FSRS#
N.C.
N.C.
N.C.
2
N.C.
3
N.C.
4
TXRDYA#
5
IRTXA
6
DSRA#
7
CTSA#
8
DTRA#
9
VCC
10
RTSA#
11
IRQ#
12
CS#
13
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
TXA
14
R/W#
15
XR16C854
100-pin QFP
16 Mode
Connect 16/68# pin to VCC
XR16C854
100-pin QFP
68 Mode
Connect 16/68# pin to GND
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
F
OR
100-
PIN
QFP P
ACKAGES
I
N
16
AND
68 M
ODE
2
39
40
41
38
49
50
44
42
48
45
43
46
47
TXB
16
A3
17
N.C.
18
RTSB#
19
GND
20
DTRB#
21
CTSB#
22
DSRB#
23
IRTXB
24
TXRDYB#
25
N.C.
26
N.C.
27
N.C.
28
N.C.
29
N.C.
30
31
A0
A1
RXC
GND
RIC#
CDC#
XTAL2
XTAL1
TXRDY#
RXRDY#
RESET#
CHCCLK
RXRDYC#
32
34
35
36
33
37
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A2
RXB
RIB#
A2
A1
A0
CDB#
16/68#
RXB
RXC
CDC#
RIB#
GND
RIC#
CLKSEL
CDB#
XTAL1
XTAL2
16/68#
RESET
RXRDYB#
CLKSEL
TXRDY#
RXRDY#
CHCCLK
REV. 3.1.0
RXRDYB#
RXRDYC#
XR16C854/854D
REV. 3.1.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
F
IGURE
3. P
IN
O
UT
A
SSIGNMENT
F
OR
PLCC P
ACKAGES
I
N
16
AND
68 M
ODE AND
LQFP P
ACKAGES
INTSEL
CDD#
CDA#
RID#
GND
RIA#
GND
RXD
VCC
RXA
D7
D6
D5
D4
D3
D2
D1
D0
68
67
66
65
64
63
62
68
67
66
65
64
63
62
63
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
60
59
58
57
56
55
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TXC
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
DSRC#
DSRA#
CTSA#
DTRA#
VCC
RTSA#
IRQ#
CS#
TXA
R/W#
TXB
A3
N.C.
RTSB#
GND
DTRB#
CTSB#
DSRB#
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
61
60
59
58
57
56
55
9
8
7
6
5
4
3
2
9
8
7
6
5
4
3
2
1
1
CDD#
CDA#
RID#
GND
RIA#
VCC
RXD
RXA
D7
D6
D5
D4
D3
D2
D1
D0
DSRD#
CTSD#
DTRD#
GND
RTSD#
N.C.
N.C.
TXD
N.C.
TXC
A4
N.C.
RTSC#
VCC
DTRC#
CTSC#
DSRC#
XR16C854
68-pin PLCC
16 Mode
(16/68# pin connected to VCC)
54
53
52
51
50
49
48
47
46
45
44
XR16C854
68-pin PLCC
68 Mode
(16/68# pin connected to GND)
54
53
52
51
50
49
48
47
46
45
44
RXRDY#
GND
RXC
RXRDY#
TXRDY#
CLKSEL
RESET#
CLKSEL
RESET
56
52
64
60
54
62
61
59
57
55
51
63
58
53
50
DSRA#
CTSA#
DTRA#
VCC
RTSA#
INTA
CSA#
TXA
IOW#
TXB
CSB#
INTB
RTSB#
GND
DTRB#
CTSB#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
21
29
22
23
25
26
27
28
30
31
17
20
18
19
24
32
49
CDD#
CDA#
GND
RID#
RIA#
D3
D0
VCC
D7
D2
D6
D5
D4
D1
RXD
RXA
48
47
46
45
44
DSRD#
CTSD#
DTRD#
GND
RTSD#
INTD
CSD#
TXD
IOR#
TX
C
CSC#
INTC
RTSC#
VCC
DTRC#
CTSC#
XR16C854
XR16C854D
64-pin LQFP
16 Mode only
43
42
41
40
39
38
37
36
35
34
33
CLKSEL
CDC#
RIB#
RESET
3
DSRC#
DSRB#
CDB#
XTAL1
XTAL2
GND
RIC#
A2
A1
A0
RXB
RXC
TXRDY#
XTAL1
XTAL1
16/68#
XTAL2
XTAL2
16/68#
CDC#
CDB#
CDC#
CDB#
RIC#
RIB#
GND
RIC#
RIB#
RXB
A2
A1
RXB
RXC
A2
A1
A0
A0
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
ORDERING INFORMATION
P
ART
N
UMBER
XR16C854CJ-F
XR16C854CJTR-F
XR16C854IJ-F
XR16C854IJTR-F
XR16C854CV-F
XR16C854CVTR-F
XR16C854IV-F
XR16C854IVTR-F
XR16C854DCV-F
XR16C854DCVTR-F
XR16C854DIV-F
XR16C854DIVTR-F
XR16C854CQ-F
XR16C854CQTR-F
XR16C854IQ-F
XR16C854IQTR-F
P
ACKAGE
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
68-Lead PLCC
64-Lead LQFP
64-Lead LQFP
64-Lead LQFP
64-Lead LQFP
64-Lead LQFP
64-Lead LQFP
64-Lead LQFP
64-Lead LQFP
100-Lead QFP
100-Lead QFP
100-Lead QFP
100-Lead QFP
O
PERATING
T
EMPERATURE
R
ANGE
0° to +70°
C
C
0° to +70°
C
C
-40° to +85°
C
C
-40° to +85°
C
C
0° to +70°
C
C
0° to +70°
C
C
-40° to +85°
C
C
-40° to +85°
C
C
0° to +70°
C
C
0° to +70°
C
C
-40° to +85°
C
C
-40° to +85°
C
C
0° to +70°
C
C
0° to +70°
C
C
-40° to +85°
C
C
-40° to +85°
C
C
D
EVICE
S
TATUS
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
Active
REV. 3.1.0
N
OTE
: TR = Tape and Reel, -F = Green / RoHS
PIN DESCRIPTIONS
Pin Description
N
AME
64-LQFP 68-PLCC 100-QFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
22
23
24
60
59
58
57
56
55
54
53
32
33
34
5
4
3
2
1
68
67
66
37
38
39
95
94
93
92
91
90
89
88
I
Address data lines [2:0]. These 3 address lines select one of the
internal registers in UART channel A-D during a data bus transac-
tion.
Data bus lines [7:0] (bidirectional).
I/O
4
XR16C854/854D
REV. 3.1.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
Pin Description
N
AME
IOR#
(N.C.)
64-LQFP 68-PLCC 100-QFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
40
52
66
I
D
ESCRIPTION
When 16/68# pin is at logic 1, the Intel bus interface is selected
and this input becomes read strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data byte from
an internal register pointed by the address lines [A2:A0], puts the
data byte on the data bus to allow the host processor to read it on
the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input is not used.
When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input becomes read (logic 1) and write (logic 0)
signal. Motorola bus interface is not available on the 64 pin pack-
age.
When 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1, this input is chip select B (active low)
to enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1, this input is chip select C (active low)
to enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
When 16/68# pin is at logic 1, this input is chip select D (active low)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used.
Motorola bus interface is not available on the 64 pin package.
IOW#
(R/W#)
9
18
15
I
CSA#
(CS#)
7
16
13
I
CSB#
(A3)
11
20
17
I
CSC#
(A4)
38
50
64
I
CSD#
(N.C.)
42
54
68
I
INTA
(IRQ#)
6
15
12
O When 16/68# pin is at logic 1 for Intel bus interface, this ouput
(OD) becomes channel A interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set to
the active mode when MCR[3] is set to a logic 1. INTA is set to the
three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
Motorola bus interface is not available on the 64 pin package.
5
