XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
JUNE 2009
REV. 1.1.1
GENERAL DESCRIPTION
The XR16M752/XR68M752
1
(M752) is a high
performance dual universal asynchronous receiver
and transmitter (UART) with 64 byte TX and RX
FIFOs. The M752 operates from 1.62 to 3.63 volts. It
is pin-to-pin and software compatible to the
TL16C752B and SC16C752B, but with additional
features such as a programmable fractional baud rate
generator, automatic RS-485 half-duplex direction
control, infrared mode and 8X and 4X sampling rate.
The standard features include 16 selectable TX and
RX FIFO trigger levels, automatic hardware (RTS/
CTS) and software (Xon/Xoff) flow control, and a
complete modem interface. Onboard registers
provide the user with operational status and data
error flags. An internal loopback capability allows
system diagnostics. Each channel is independently
programmable for data rates up to 16 Mbps at 3.3V
with a 4X sampling rate. The XR68M752 has an
additional 16/68# pin to select between the Intel and
Motorola bus interface. The M752 is available in the
48-pin TQFP, 32-pin QFN and 49-pin STBGA
packages.
N
OTE
:
1 Covered by U.S. Patent #5,649,122
FEATURES
•
1.62 to 3.6 Volt Operation
•
Pin-to-pin and software compatible to TI’s
TL16C752B and Philips’ SC16C752B in the 48-
TQFP package
•
Two independent UART channels
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Data rate of up to
16 Mbps at 3.3 V
Data rate of up to
12.5 Mbps at 2.5 V
Data rate of up to
8 Mbps at 1.8 V
Fractional Baud Rate Generator
Data sampling rates of 16X, 8X and 4X
Transmit and Receive FIFOs of 64 bytes
Programmable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Halt and Resume Transmission Control
Automatic RS-485 Half-duplex Direction
Control Output via RTS#
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Automatic sleep mode
Full modem interface
APPLICATIONS
•
Crystal oscillator (up to 24MHz) or external clock
(up to 64MHz) input
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16M752 B
LOCK
D
IAGRAM
•
48-TQFP, 32-QFN and 49-STBGA packages
A2:A0
D7:D0
IOR# (NC)
IOW# (R/W#)
CSA# (CS#)
CSB# (A3)
INTA (IRQ#)
INTB (NC)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
Reset/Reset#
16/68#
8-bit Data
Bus
Interface
UART Channel A
UART
Regs
BRG
64 Byte TX FIFO
TX & RX
IR
ENDEC
1.62 to 3.63 Volt VCC
GND
TXA, RXA, DTRA#,
DSRA#, RTSA#,
DTSA#, CDA#, RIA#,
OP2A#
64 Byte RX FIFO
TXB, RXB, DTRB#,
DSRB#, RTSB#,
CTSB#, CDB#, RIB#,
OP2B#
XTAL1
XTAL2
UART Channel B
(same as Channel A)
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
F
IGURE
2. P
IN
O
UT
A
SSIGNMENT
- TQFP
AND
QFN P
ACKAGES
TXRDYA#
DSRA#
CTSA#
REV. 1.1.1
VCC
RIA#
CDA#
48
45
43
42
41
40
38
47
46
44
39
37
NC
D4
D3
D2
D1
D0
D1
31 D4
30 D3
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
NC
2
3
4
5
6
7
8
9
10
11
12
15
13
18
19
20
22
16
14
17
21
23
24
35
34
33
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
32 D5
29 D2
27
D0
26
VCC
D5
1
36
RESET
28
25
CTSA#
D6
D7
RXB
RXA
TXA
TXB
CSA#
CSB#
1
2
3
4
5
6
7
8
GND 13
CTSB# 16
XTAL2 11
IOR# 14
RTSB# 15
XTAL1 10
IOW# 12
9
XR16M752
32-pin QFN
Intel Mode Only
24
23
22
21
20
19
18
17
RESET
RTSA#
INTA
INTB
A0
A1
A2
NC
XR16M752
48-pin TQFP
Intel Mode Only
32
31
30
29
28
27
26
25
RXRDYB#
DSRB#
CDB#
GND
RIB#
RTSB#
TXRDYA#
DSRA#
CTSB#
XTAL2
XTAL1
IOW#
IOR#
VCC
CTSA#
RIA#
CDA#
NC
48
40
38
45
43
42
47
46
44
41
39
37
NC
D4
D3
D2
D1
D0
NC
D1
31 D4
30 D3
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA #
CSB #
NC
2
3
4
5
6
7
8
9
10
11
12
15
18
19
20
22
13
16
17
21
23
14
24
35
34
33
32
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA #
INTA
INTB
A0
A1
A2
NC
32 D5
29 D2
27
D0
26
VCC
D5
1
36
RESET
28
25
CTSA#
D6
D7
RXB
RXA
TXA
TXB
CSA#
CSB#
1
2
3
4
5
6
7
8
GND 13
CTSB# 16
XTAL2 11
IOR# 14
RTSB# 15
XTAL1 10
IOW# 12
9
XR68M752
32-pin QFN
Intel Mode
24
23
22
21
20
19
18
17
RESET
RTSA#
INTA
INTB
A0
A1
A2
16/68#
VCC
XR68M 752
48- pin TQFP
Intel Mode
31
30
29
28
27
26
25
RXRDYB#
DSRB#
CDB#
RTSB#
CTSB#
XTAL2
XTAL1
16/68#
GND
IOW#
IOR#
RIB#
VCC
TXRDYA#
DSRA#
VCC
CTSA#
RIA#
CDA#
48
40
38
45
43
42
47
46
44
41
39
37
NC
D4
D3
D2
D1
D0
NC
D1
31 D4
30 D3
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CS#
A3
NC
27
26
2
3
4
5
6
7
8
9
10
11
12
15
13
18
19
20
22
16
14
17
21
23
24
34
33
32
DTRA#
RTSA#
OP2A#
RXRDYA #
IRQ#
NC
A0
A1
A2
NC
28
25
24
23
22
35
DTRB#
D6
D7
RXB
RXA
TXA
TXB
CS#
A3
1
2
3
4
5
6
7
8
32 D5
1
29 D2
RESET#
D0
36
CTSA#
VCC
RESET#
RTSA#
IRQ#
NC
A0
A1
A2
16/68#
GND
XR68M752
48- pin TQFP
Motorola Mode
31
30
29
28
27
26
25
XR68M752
32-pin QFN
Motorola Mode
21
20
19
18
17
GND 13
RXRDYB#
CDB#
DSRB#
GND
XTAL2
RTSB#
CTSB#
XTAL1
16/68#
R/W#
RIB#
NC
GND
2
CTSB# 16
XTAL2 11
14
NC
RTSB# 15
XTAL1 10
R/W#
NC
12
9
XR16M752/XR68M752
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
F
IGURE
3. P
IN
O
UT
A
SSIGNMENT
- STBGA P
ACKAGE
A1 Corner
1 2
A
B
C
D
E
F
G
Transparent Top View
NC
D5
D6
TXB
CSB#
PWRSAVE
XTAL1
D3
D4
D7
RXA
CSA#
IOW#
XTAL2
D0
D1
RXB
TXA
OP2B#
CDB#
GND
RIA#
D2
TXRDYA#
TXRDYB#
RIB#
RXRDYB#
IOR#
CTSA#
VCC
CDA#
RTSA#
RXRDYA#
DSRB#
RTSB#
RS485#
DSRA#
OP2A#
INTA
A0
CTSB#
16/68#
DTRA#
RESET
DTRB#
INTB
A1
ENIR#
A2
3 4
5 6 7
ORDERING INFORMATION
P
ART
N
UMBER
XR16M752IL32
XR16M752IM48
XR68M752IL32
XR68M752IM48
XR68M752IB49
P
ACKAGE
32-pin QFN
48-Lead TQFP
32-pin QFN
48-Lead TQFP
49-pin STBGA
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
Active
3
XR16M752/XR68M752
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
REV. 1.1.1
PIN DESCRIPTIONS
Pin Description
N
AME
32-QFN
P
IN
#
48-TQFP
P
IN
#
49-STBGA
P
IN
#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(NC)
18
19
20
2
1
32
31
30
29
28
27
14
26
27
28
3
2
1
48
47
46
45
44
19
G7
E7
E6
C2
C1
B1
B2
A2
B4
B3
A3
G4
I
Address data lines [2:0]. These 3 address lines select
one of the internal registers in UART channel A/B during
a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is HIGH, the Intel bus interface is
selected and this input becomes read strobe (active low).
The falling edge instigates an internal read cycle and
retrieves the data byte from an internal register pointed
by the address lines [A2:A0], puts the data byte on the
data bus to allow the host processor to read it on the ris-
ing edge.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input is not used.
When 16/68# pin is HIGH, it selects Intel bus interface
and this input becomes write strobe (active low). The fall-
ing edge instigates the internal write cycle and the rising
edge transfers the data byte on the data bus to an inter-
nal register pointed by the address lines.
When 16/68# pin is LOW, the Motorola bus interface is
selected and this input becomes read (HIGH) and write
(LOW) signal.
When 16/68# pin is HIGH, this input is chip select A
(active low) to enable channel A in the device.
When 16/68# pin is LOW, this input becomes the chip
select (active low) for the Motorola bus interface.
When 16/68# pin is HIGH, this input is chip select B
(active low) to enable channel B in the device.
When 16/68# pin is LOW, this input becomes address
line A3 which is used for channel selection in the Motor-
ola bus interface. Input logic 0 selects channel A and
logic 1 selects channel B.
IOW#
(R/W#)
12
15
F2
I
CSA#
(CS#)
7
10
E2
I
CSB#
(A3)
8
11
E1
I
4
XR16M752/XR68M752
REV. 1.1.1
HIGH PERFORMANCE DUART WITH 64-BYTE FIFO
Pin Description
N
AME
INTA
(IRQ#)
32-QFN
P
IN
#
22
48-TQFP
P
IN
#
30
49-STBGA
P
IN
#
D6
T
YPE
O
D
ESCRIPTION
When 16/68# pin is HIGH for Intel bus interface, this out-
put becomes channel A interrupt output. The output state
is defined by the user through the software setting of
MCR[3]. INTA is set to the active mode and OP2A# out-
put LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to HIGH when MCR[3]
is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this
output becomes device interrupt output (active low, open
drain). An external pull-up resistor is required for proper
operation.
When 16/68# pin is HIGH for Intel bus interface, this out-
put becomes channel B interrupt output. The output state
is defined by the user through the software setting of
MCR[3]. INTB is set to the active mode and OP2A# out-
put to LOW when MCR[3] is set to a logic 1. INTA is set to
the three state mode and OP2A# to HIGH when MCR[3]
is set to a logic 0. See MCR[3].
When 16/68# pin is LOW for Motorola bus interface, this
output is not used.
UART channel A Transmitter Ready (active low). The
output provides the TX FIFO/THR status for transmit
channel A. See
Table 3
. If it is not used, leave it uncon-
nected.
UART channel A Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
A. See
Table 3
. If it is not used, leave it unconnected.
UART channel B Transmitter Ready (active low). The
output provides the TX FIFO/THR status for transmit
channel B. See
Table 4
. If it is not used, leave it uncon-
nected.
UART channel B Receiver Ready (active low). This out-
put provides the RX FIFO/RHR status for receive channel
B. See
Table 3
. If it is not used, leave it unconnected.
INTB
(NC)
21
29
D7
O
TXRDYA#
-
43
C4
O
RXRDYA#
-
31
E5
O
TXRDYB#
-
6
D4
O
RXRDYB#
-
18
F4
O
MODEM OR SERIAL I/O INTERFACE
TXA
5
7
D3
O
UART channel A Transmit Data or infrared encoder data.
Standard transmit and receive interface is enabled when
MCR[6] = 0. In this mode, the TX signal will be HIGH dur-
ing reset or idle (no data). Infrared IrDA transmit and
receive interface is enabled when MCR[6] = 1. In the
Infrared mode, the inactive state (no data) for the Infrared
encoder/decoder interface is LOW. If it is not used, leave
it unconnected.
5
