xr
AUGUST 2005
XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
REV. 1.2.2
GENERAL DESCRIPTION
The XR17D154
1
(D154) is a quad PCI Bus Universal
Asynchronous Receiver and Transmitter (UART) with
same package and pin-out as the Exar XR17C158,
XR17D158 and XR17C154. The device is designed
to meet today’s 32-bit PCI Bus and high bandwidth
requirement in communication systems. The global
interrupt source register provides a complete interrupt
status indication for all 4 channels to speed up
interrupt parsing. Each UART is independently
controlled and has its own 16C550 compatible 5G
register set, transmit and receive FIFOs of 64 bytes,
fully programmable transmit and receive FIFO trigger
levels, transmit and receive FIFO level counters,
automatic hardware flow control with programmable
hysteresis, automatic software (Xon/Xoff) flow
control, IrDA (Infrared Data Association) encoder/
decoder, 8 multi-purpose inputs/outputs and a 16-bit
general purpose timer/counter.
N
OTE
:
1 Covered by U.S. Patents #5,649,122, #5,949,787
FEATURES
•
High Performance Quad PCI UART
•
Universal PCI Bus Buffers - Auto-sense 3.3V or 5V
Operation
•
32-bit PCI Bus 2.3 Target Signalling Compliance
•
A Global Interrupt Source Register for all 4 UARTs
•
Data Transfer in Byte, Word and Double-word
•
Data Read/Write Burst Operation
•
Each UART is independently controlled with:
■
■
■
■
■
■
■
■
■
APPLICATIONS
•
Universal Form Factor PCI Bus Add-in Card
•
Remote Access Servers
•
Ethernet Network to Serial Ports
•
Network Management
•
Factory Automation and Process Control
•
Point-of-Sale Systems
•
Multi-port RS-232/RS-422/RS-485 Cards
F
IGURE
1. B
LOCK
D
IAGRAM
3.3V or 5V
(PCI VI/O
Power Supply)
CLK (33MHz)
RST#
AD[31:0]
C/BE[3:0]#
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
INTA#
IDSEL
PERR#
SERR#
PAR
16C550 Compatible 5G Register Set
64-byte Transmit and Receive FIFOs
Transmit and Receive FIFO Level Counters
Automatic RTS/CTS or DTR/DSR Flow Control
Automatic Xon/Xoff Software Flow Control
Automatic RS485 Half-duplex Control Output
with Selectable Turn-around Delay
Infrared (IrDA 1.0) Data Encoder/Decoder
Programmable Data Rate with Prescaler
Up to 6.25 Mbps Serial Data Rate at 8X
•
Eight Multi-Purpose Inputs/outputs
•
General Purpose 16-bit Timer/Counter
•
Sleep Mode with Automatic Wake-up
•
EEPROM Interface for PCI Configuration
•
Same package and pin-out as the XR17D158,
XR17C158 and
LQFP)
XR17C154 (20x20x1.4mm 144-
VCC (Core
Logic)
GND
UART Channel 0
UART
Regs
64 Byte TX FIFO
TX & RX
IR
ENDEC
PCI Local
Bus
Interface
TX0, RX0, DTR0#,
DSR0#, RTS0#,
CTS0#, CD0#, RI0#
Device
Configuration
Registers
BRG
64 Byte RX FIFO
UART Channel 1
UART Channel 2
Configuration
Space
Registers
TX3, RX3, DTR3#,
DSR3#, RTS3#,
CTS3#, CD3#, RI3#
MPIO0- MPIO7
XTAL1
XTAL2
TMRCK
UART Channel 3
EECK
EEDI
EEDO
EECS
ENIR
EEPROM
Interface
16-bit
Timer/Counter
Multi-purpose
.
Inputs/Outputs
Crystal Osc/Buffer
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
F
IGURE
2. P
IN
O
UT OF THE
D
EVICE
DTR1#
DSR1#
MPIO0
MPIO1
DTR2#
DSR2#
RTS1#
CTS1#
RTS2#
CD1#
CD2#
CTS2#
VCC
RI1#
RI2#
RX1
xr
REV. 1.2.2
TX2
TX1
107
104
103
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
108
106
105
102
79
78
77
76
75
74
MPIO2
GND
XTAL2
XTAL1
TEST#
VCC
EEDO
EEDI
EECS
EECK
NC
NC
NC
NC
NC
NC
NC
NC
TX0
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
MPIO3
RX2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
NC
NC
ENIR
TMRCK
MPIO4
MPIO5
MPIO6
MPIO7
VCC
GND
TX3
DTR3#
RTS3#
RI3#
CD3#
DSR3#
CTS3#
RX3
NC
NC
NC
NC
NC
NC
NC
NC
GND
VIO
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
DTR0# 126
RTS0# 127
RI0#
CD0#
128
129
XR17D154
144-LQFP
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
29
24
CBE1 25
28
30
31
32
33
34
35
GND
DSR0# 130
CTS0# 131
RX0
INTA#
RST#
CLK
GND
VIO
AD31
AD30
AD29
AD28
AD27
AD26
AD25
132
133
134
135
136
137
138
139
140
141
142
143
144
11
21
PERR# 22
SERR# 23
13
CBE2 14
FRAME# 15
16
TRDY# 17
DEVSEL# 18
19
AD17 12
20
10
26
27
36
CBE0
2
4
5
1
6
7
8
3
9
CBE3
IDSEL
STOP#
AD24
AD23
AD22
AD20
AD19
AD16
AD21
AD18
AD15
AD14
AD13
AD12
IRDY#
AD11
AD10
GND
GND
PAR
ORDERING INFORMATION
P
ART
N
UMBER
XR17D154CV
XR17D154IV
P
ACKAGE
144-Lead LQFP
144-Lead LQFP
O
PERATING
T
EMPERATURE
R
ANGE
0°C to +70°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
2
AD9
AD8
VIO
VIO
VIO
xr
REV. 1.2.2
XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
PIN DESCRIPTIONS
N
AME
P
IN
#
T
YPE
D
ESCRIPTION
PCI LOCAL BUS INTERFACE
RST#
134
I
PCI Bus reset input (active low). It resets the PCI local bus configuration
space registers, device configuration registers and UART channel registers
to the default condition.
PCI Bus clock input of up to 33.34MHz.
Address data lines [31:0] (bidirectional).
CLK
AD31-AD25,
AD24,
AD23-AD16,
AD15-AD8,
AD7-AD0
FRAME#
C/BE3#-
C/BE0#
IRDY#
TRDY#
STOP#
IDSEL
DEVSEL#
INTA#
PAR
PERR#
SERR#
135
138-144,
1,
6-13
26-33
37-44
15
2,14,25,36
16
17
21
3
18
133
24
22
23
I
IO
I
I
I
O
O
I
O
OD
IO
O
OD
Bus transaction cycle frame (active low). It indicates the beginning and dura-
tion of an access.
Bus Command/Byte Enable [3:0] (active low). This line is multiplexed for bus
Command during the address phase and Byte Enable during the data phase.
Initiator Ready (active low). During a write, it indicates valid data is present
on data bus. During a read, it indicates the master is ready to accept data.
Target Ready (active low).
Target request to stop current transaction (active low). 5
Initialization device select (active high).
Device select to the XR17D154 (active low).
Device interrupt from XR17D154 (open drain, active low).
Parity is even across AD[31:0] and C/BE[3:0]# (bidirectional, active high).
Parity error indicator to host (active low). Optional in bus target application.
System error indicator to host (open drain, active low). Optional in bus target
application.
UART channel 0 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
UART channel 0 Receive Data or infrared receive data. Normal RXD input
idles HIGH. The infrared pulses typically idle LOW but can be inverted inter-
nally prior the decoder by FCTR[4].
UART channel 0 Request to Send or general purpose output (active low).
UART channel 0 Clear to Send or general purpose input (active low).
UART channel 0 Data Terminal Ready or general purpose output (active
low).
UART channel 0 Data Set Ready or general purpose input (active low).
UART channel 0 Carrier Detect or general purpose input (active low).
UART channel 0 Ring Indicator or general purpose input (active low).
MODEM OR SERIAL I/O INTERFACE
TX0
RX0
125
132
O
I
RTS0#
CTS0#
DTR0#
DSR0#
CD0#
RI0#
127
131
126
130
129
128
O
I
O
I
I
I
3
XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
xr
REV. 1.2.2
PIN DESCRIPTIONS
N
AME
TX1
RX1
P
IN
#
106
99
T
YPE
O
I
D
ESCRIPTION
UART channel 1 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
UART channel 1 Receive Data or infrared receive data. Normal RXD input
idles HIGH. The infrared pulses typically idle LOW but can be inverted inter-
nally prior the decoder by FCTR[4].
UART channel 1 Request to Send or general purpose output (active low).
UART channel 1 Clear to Send or general purpose input (active low).
UART channel 1 Data Terminal Ready or general purpose output (active
low).
UART channel 1 Data Set Ready or general purpose input (active low).
UART channel 1 Carrier Detect or general purpose input (active low).
UART channel 1 Ring Indicator or general purpose input (active low).
UART channel 2 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
UART channel 2 Receive Data or infrared receive data. Normal RXD input
idles HIGH. The infrared pulses typically idle LOW but can be inverted inter-
nally prior the decoder by FCTR[4].
UART channel 2 Request to Send or general purpose output (active low).
UART channel 2 Clear to Send or general purpose input (active low).
UART channel 2 Data Terminal Ready or general purpose output (active
low).
UART channel 2 Data Set Ready or general purpose input (active low).
UART channel 2 Carrier Detect or general purpose input (active low).
UART channel 2 Ring Indicator or general purpose input (active low).
UART channel 3 Transmit Data or infrared transmit data. Normal TXD output
idles HIGH while infrared TXD output idles LOW.
UART channel 3 Receive Data or infrared receive data. Normal RXD input
idles HIGH. The infrared pulses typically idle LOW but can be inverted inter-
nally prior the decoder by FCTR[4].
UART channel 3 Request to Send or general purpose output (active low).
UART channel 3 Clear to Send or general purpose input (active low).d.
UART channel 3 Data Terminal Ready or general purpose output (active
low).
UART channel 3 Data Set Ready or general purpose input (active low).
UART channel 3 Carrier Detect or general purpose input (active low).
UART channel 3 Ring Indicator or general purpose input (active low).
RTS1#
CTS1#
DTR1#
DSR1#
CD1#
RI1#
TX2
RX2
104
100
105
101
102
103
88
81
O
I
O
I
I
I
O
I
RTS2#
CTS2#
DTR2#
DSR2#
CD2#
RI2#
TX3
RX3
86
82
87
83
84
85
62
55
O
I
O
I
I
I
O
I
RTS3#
CTS3#
DTR3#
DSR3#
CD3#
RI3#
ANCILLARY SIGNALS
MPIO0
60
56
61
57
58
59
O
I
O
I
I
I
108
I/O
Multi-purpose input/output 0. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
4
xr
REV. 1.2.2
XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
PIN DESCRIPTIONS
N
AME
MPIO1
MPIO2
MPIO3
MPIO4
MPIO5
MPIO6
MPIO7
EECK
P
IN
#
107
74
73
68
67
66
65
116
T
YPE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
D
ESCRIPTION
Multi-purpose input/output 1. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 2. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 3. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 4. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 5. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 6. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Multi-purpose input/output 7. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
Serial clock to EEPROM. An internal clock of CLK divide by 256 is used for
reading the vendor and sub-vendor ID and model number during power up or
reset. However, it can be manually clocked thru the Configuration Register
REGB.
Chip select to a EEPROM device like 93C46. It is manually selectable thru
the Configuration Register REGB. Requires a pull-up 4.7KΩ resistor for
external sensing of EEPROM during power up. See DAN112 for further
details.
Write data to EEPROM device. It is manually accessible thru the Configura-
tion Register REGB. The D154 auto-configuration register interface logic
uses the 16-bit format.
Read data from EEPROM device. It is manually accessible thru the Configu-
ration Register REGB.
Crystal of up to 24MHz or external clock input of up to 50MHz for data rates
up to 6.25Mbps at 5V and 8X sampling. See AC Characterization table. Cau-
tion: this input is not 5V tolerant at 3.3V.
Crystal or buffered clock output.
16-bit timer/counter external clock input.
Infrared mode enable (active high). This pin is sampled during power up, fol-
lowing a hardware reset (RST#) or soft-reset (register RESET). It can be
used to start up all 4 UARTs in the infrared mode. The sampled logic state is
transferred to MCR bit-6 in the UART. Software can override this pin thereaf-
ter and enable or disable it.
Factory Test. Connect to VCC for normal operation.
5V or 3.3V power supply for the core logic. This power supply determines
the VOH level of the non-PCI bus interface outputs. Note that
VCC
≥
VIO
for
normal device operation and see
Table 1
for valid combinations of VCC and
VIO.
SEE”APPLICATION EXAMPLES” ON PAGE 8.
However,
VCC must
equal VIO
if sleep mode is used. See
Sleep Mode
section on
page 19.
EECS
115
O
EEDI
114
O
EEDO
XTAL1
113
110
I
I
XTAL2
TMRCK
ENIR
109
69
70
O
I
I
TEST#
VCC
111
64, 90, 112
I
PWR
5
