XR19L402
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
JUNE 2007
REV. 1.0.0
GENERAL DESCRIPTION
The XR19L402 (L402) is a highly integrated device that
combines a full-featured two channel Universal
Asynchronous Receiver and Transmitter (UART) and RS-
485 transceivers. The L402 is designed to operate with a
single 3.3V or 5V power supply. The L402 is fully compliant
with RS-485 Standards.
The L402 operates in four different modes: Active, Partial
Sleep, Full Sleep and Power-Save. Each mode can be
invoked via hardware or software. Upon power-up, the
L402 is in the Active mode where the UART and RS-485
transceiver function normally. In the Partial Sleep mode, the
internal crystal oscillator of the UART or charge pump of the
RS-485 transceiver is turned off. In Full Sleep mode, both
the crystal oscillator and the charge pump are turned off.
While the UART is in the Sleep mode, the Power-Save
mode isolates the core logic from the control signals (chip
select, read/write strobes, address and data bus lines) to
minimize the power consumption. The RS-485 receivers
remain active in any of these four modes.
APPLICATIONS
•
Battery-Powered Equipment
•
Handheld and Mobile Devices
•
Handheld Terminals
•
Industrial Peripheral Interfaces
•
Point-of-Sale (POS) Systems
FEATURES
•
Meets true RS-485 Standards at 3.3V or 5V operation
•
Up to 8 Mbps data transmission rate
•
45us sleep mode exit (charge pump to full power)
•
ESD protection for RS-485 I/O pins at
■
■
■
+/-15kV - Human Body Model
+/- 8kV - IEC 1000-4-2, Contact Discharge
+/- 15kV - IEC 61000-4-2, Air-Gap Discharge
•
Software compatible with industry standard 16550 UART
•
Intel/Motorola bus select
•
Complete modem interface
•
Sleep and Power-save modes to conserve battery power
•
Wake-up interrupt upon exiting low power modes
F
IGURE
1. B
LOCK
D
IAGRAM
VCC33
XTAL1
XTAL2
VCC50
R_EN
GND
ACP
C1+
Intel or Motorola Bus Interface
PwrSave
A2:A0
D7:D0
IOR#
IOW# (R/W#)
CSA# (CS#)
CSB#
INTA (IRQ#)
INTB
RESET (RESET#)
I/M#
TEST_EN
HALF/FULLA#
HALF/FULLB#
*5 V Tolerant
Inputs
Crystal
Osc/Buffer
BRG
Charge Pump
TXA+
TXA-
RXA+
RXA-
64 Byte
TX FIFO
UART Registers
64 Byte
RX FIFO
TXA
RXA
VCC33
Modem
I/Os
CTSA#
DSRA#
RIA#
CDA#
TXB
RXB
RS-485 Transceiver
Channel A
Channel B
( Similar to
ChannelA )
UART
C1-
TXB+
TXB-
RXB+
RXB-
TXB
RXB
RXBSEL
XR19L402
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR19L402
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
F
IGURE
2. P
IN
O
UT OF THE
D
EVICE
REV. 1.0.0
41 HALF/FULLA#
40 HALF/FULLB#
42 TEST_EN
44 RXBSEL
39 VDD50
46 INTA
45 INTB
TXA+
38
37 GND
48
43 RXB
A1
47
A2
A0
D0
1
2
36
35
34
33
32
31
30
29
28
27
26
25
ACP 20
R_EN 21
VDD33 22
TXB+ 23
IOR# 16
RESET 19
XTAL2 14
XTAL1 13
IOW# 15
GND 24
TXB 17
I/M# 18
TXA-
NC
RXA+
RXA-
NC
C1+
C1-
NC
RXB-
RXB+
NC
TXB-
D1 3
D2 4
D3 5
D4
D5
6
7
D6 8
D7 9
CSA# 10
CSB # 11
PW RSAVE 12
XR19L 402
48 - pin QFN
Intel Bus Mode
VCC
40 HALF/FULLB#
41 HALF/FULLA#
42 TEST_EN
44 RXBSEL
39 VCC50
38 TXA+
46 IRQ#
37 GND
48
43 RXB
45 NC
A1
47
A2
A0
D0
1
2
36
35
34
33
32
31
30
29
28
27
26
25
ACP 20
R_EN 21
VCC33 22
TXB+ 23
RESET# 19
XTAL2 14
XTAL1 13
R/W# 15
GND 24
NC 16
TXB 17
I/M# 18
TXA-
NC
RXA+
RXA-
NC
C1+
C1-
NC
RXB-
RXB+
NC
TXB-
D1 3
D2 4
D3 5
D4
D5
6
7
D6 8
D7 9
CS# 10
A3 11
PW RSAVE 12
XR19L 402
48 - pin QFN
Motorola Bus Mode
GND
ORDERING INFORMATION
P
ART
N
UMBER
XR19L402IL48
P
ACKAGE
48-pin QFN
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
D
EVICE
S
TATUS
Active
2
XR19L402
REV. 1.0.0
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
PIN DESCRIPTIONS
Pin Descriptions
N
AME
48-QFN
PIN#
T
YPE
D
ESCRIPTION
DATA BUS INTERFACE (CMOS/TTL Voltage Levels)
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(NC)
47
48
1
9
8
7
6
5
4
3
2
16
I
Address bus lines [2:0]. These 3 address lines select one of the internal registers in the
UART during a data bus transaction.
Data bus lines [7:0] (bidirectional).
I/O
I
When I/M# pin is HIGH, the Intel bus interface is selected and this input becomes read
strobe (active LOW). The falling edge instigates an internal read cycle and retrieves the
data byte from an internal register pointed by the address lines [A2:A0], puts the data byte
on the data bus to allow the host processor to read it on the rising edge.
When I/M# pin is LOW, the Motorola bus interface is selected and this input is not used.
When I/M# pin is HIGH, it selects Intel bus interface and this input becomes write strobe
(active LOW). The falling edge instigates the internal write cycle and the rising edge trans-
fers the data byte on the data bus to an internal register pointed by the address lines.
When I/M# pin is LOW, the Motorola bus interface is selected and this input becomes read
(HIGH) and write (LOW) signal.
When I/M# pin is HIGH, this input is chip select A (active low) to enable channel A in the
device.
When I/M# pin is LOW, this input becomes the chip select (active low) for the Motorola bus
interface.
When I/M# pin is HIGH, this input is chip select B (active low) to enable channel B in the
device.
When I/M# pin is LOW, this input becomes address line A3 which is used for channel selec-
tion in the Motorola bus interface. Input logic 0 selects channel A and logic 1 selects chan-
nel B.
IOW#
(R/W#)
15
I
CSA#
(CS#)
10
I
CSB#
(A3)
11
I
INTA
(IRQ#)
46
O When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
(OD) HIGH device interrupt output for channel A. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output becomes the active
LOW, open-drain interrupt output for both channels. An external pull-up resistor is required
for proper operation. MCR[3] must be set to a logic 0 for proper operation of the interrupt.
O When I/M# pin is HIGH, it selects Intel bus interface and this output become the active
(OD) HIGH device interrupt output for channel B. This output is enabled through the software set-
ting of MCR[3]: set to the active mode when MCR[3] is set to a logic 1, and set to the three
state mode when MCR[3] is set to a logic 0. See MCR[3].
When I/M# pin is LOW, it selects Motorola bus interface and this output is not used and can
be left unconnected.
INTB
(NC)
45
3
XR19L402
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
Pin Descriptions
N
AME
48-QFN
PIN#
T
YPE
D
ESCRIPTION
REV. 1.0.0
SERIAL I/O INTERFACE (RS-485/RS-485 Voltage Levels)
TXA+
TXA-
RXA+
RXA-
TXB+
TXB-
RXB+
RXB-
38
36
34
33
23
25
27
28
O
I
O
I
Differential UART Channel A Transmit Data.
Differential UART Channel A Receive Data.
Differential UART Channel B Transmit Data.
Differential UART Channel B Receive Data.
SERIAL I/O INTERFACE (CMOS/TTL Voltage Levels)
TXB
RXB
17
43
O
I
UART Channel B Transmit Data. This pin can be used to communicate with external IR or
RS-485 transceiver.
UART Channel B Receive Data. This pin can be used to communicate with external IR or
RS-485 transceiver.
ANCILLARY SIGNALS (CMOS/TTL Voltage Levels)
HALF/
FULLA#
HALF/
FULLB#
TEST_EN
XTAL1
XTAL2
PwrSave
ACP
I/M#
41
40
42
13
14
12
20
18
I
I
I
I
O
I
I
I
When HALF/FULLA# is HIGH, half-duplex mode is enabled for channel A.
When HALF/FULLA# is LOW, full-duplex mode is enabled for channel A.
When HALF/FULLB# is HIGH, half-duplex mode is enabled for channel B.
When HALF/FULLB# is LOW, full-duplex mode is enabled for channel B.
For factory test mode only. For normal operation, connect to GND.
Crystal or external clock input.
Crystal or buffered clock output.
Power-Save (active high). This feature isolates the L402’s data bus interface from the host
preventing other bus activities that cause higher power drain during sleep mode.
Autosleep for Charge Pump (active HIGH). When this pin is HIGH, the charge pump is shut
off if the UART is already in sleep mode, i.e. the XTAL2 output is LOW.
Intel or Motorola Bus Select.
When I/M# pin is HIGH, 16 or Intel Mode, the device will operate in the Intel bus type of
interface.
When I/M# pin is LOW, 68 or Motorola mode, the device will operate in the Motorola bus
type of interface.
When I/M# pin is HIGH for Intel bus interface, this input becomes RESET (active high).
When I/M# pin is LOW for Motorola bus interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers and all outputs of
the UART. The UART transmitter output will be held HIGH, the receiver input will be ignored
and outputs are reset during reset period.
Charge pump capacitors. As shown in
Figure 1
, a 0.22 uF capacitor should be placed
between these 2 pins.
When the supply voltage is < 3.6V, connect R_EN to GND.
When the supply voltage is > 3.6V, connect R_EN to VCC.
RESET
(RESET#)
19
I
C1+
C1-
R_EN
31
30
21
-
I
4
XR19L402
REV. 1.0.0
TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER
Pin Descriptions
N
AME
RXBSEL
VCC33
48-QFN
PIN#
44
22
T
YPE
I
D
ESCRIPTION
When RXBSEL is HIGH, RXB is the receive data input.
When RXBSEL is LOW, RXB+ and RXB- are the receive data inputs.
Pwr 3.3V power supply. When VCC33 is used, R_EN pin should be connected to GND and
VCC50 should be left unconnected. A 0.1 uF capacitor to GND is recommended on this
power supply pin. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
Pwr 5.0V power supply. When VCC50 is used, R_EN pin should be connected to VCC and
VCC33 should be left unconnected. A 1 uF capacitor to GND is recommended on this
power supply pin. All CMOS/TTL input pins, except XTAL1, are 5V tolerant.
Pwr Power supply common, ground.
Pwr The center pad on the backside of the 64-QFN package is metallic and is not electrically
connected to anything inside the device. It must be soldered on to the PCB and may be
optionally connected to GND on the PCB. The thermal pad size on the PCB should be the
approximate size of this center pad and should be solder mask defined. The solder mask
opening should be at least 0.0025" inwards from the edge of the PCB thermal pad.
-
No Connect. Note that in Motorola mode, the IOR# pin also becomes an NC pin.
VCC50
39
GND
-
24, 37
PAD
NC
26, 29, 32,
35
N
OTE
:
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
For CMOS/TTL Voltage levels, ’LOW’
indicates a voltage in the range 0V to VIL and ’HIGH’ indicates a voltage in the range VIH to VCC.
5
