DUAL UNIVERSAL ASYNCHRONOUS
RECEIVER AND TRANSMITTER
August 2005
XR88C92/192
DESCRIPTION
The XR88C92/192 is a Dual Universal Asynchronous Receiver and Transmitter with 8 (XR88C92) / 16 (XR88C192)
bytes transmit and receive FIFO. The XR88C92/192 is a pin and functional replacement for the SC26C92 and an
improved version of the Philips SCC2692 UART with faster data access and other additional features. The operating
speed of the receiver and transmitter can be selected independently from a table of eighteen fixed baud rates, a
16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The baud rate generator and
counter/timer can operate directly from a crystal or from external clock input. The XR88C92/192 provides a power-
down mode in which the oscillator is stopped but the register contents are retained. The XR88C92/192 is fabricated
in an advanced CMOS process to achieve low power and high speed requirements.
FEATURES
Added features in devices with top marking of "D2" and
newer:
•
5 volt tolerant inputs
•
Pin to pin and functional compatible to SC26C92
•
Enhanced Multidrop mode operation with separate
storage for address and data tags (9th bit)
•
8 Bytes transmit/receive FIFO (XR88C92)
•16
Bytes transmit/receive FIFO (XR88C192)
•
Standard baud rates from 50bps to 230.4kbps
•
Non-standard baud rate of up to 1Mbps
•
Transmit and Receive trigger levels
•
Watch dog timer
•
Programmable clock source for receiver and trans-
mitter of each channel
•
Single interrupt output
•
7 Multipurpose inputs, 8 Multipurpose outputs
•
2.97 to 5.5 volt operation
•
Programmable character lengths (5, 6, 7, 8)
•
Parity, framing, and over run error detection
•
Programmable 16-bit timer/counter
•
On-chip crystal oscillator
•
Power down mode
PLCC Package
VCC
N.C.
IP1
IP3
IP4
IP5
IP6
41
44
43
42
A3
IP0
-IOW
-IOR
RXB
N.C.
TXB
OP1
OP3
OP5
OP7
7
8
9
10
11
12
13
14
15
16
17
D1 18
D3 19
D5 20
D7 21
GND 22
N.C. 23
-INT 24
D6 25
D4 26
D2 27
D0 28
40
6
5
4
3
2
1
IP2
A2
A1
A0
39
38
37
36
35
-CS
RESET
XTAL2
XTAL1
RXA
N.C.
TXA
OP0
OP2
OP4
OP6
XR88C92
XR88C192
34
33
32
31
30
29
ORDERING INFORMATION
Part number
Package
Operating temperature Device Status
XR88C92CJ
XR88C92CV
XR88C92IJ
XR88C92IV
XR88C192CJ
XR88C192CV
XR88C192IJ
XR88C192IV
44-Lead
44-Lead
44-Lead
44-Lead
44-Lead
44-Lead
44-Lead
44-Lead
PLCC
LQFP
PLCC
LQFP
PLCC
LQFP
PLCC
LQFP
0° C
0° C
-40° C
-40° C
0° C
0° C
-40° C
-40° C
to
to
to
to
to
to
to
to
+ 70° C
+ 70° C
+ 85° C
+ 85° C
+ 70° C
+ 70° C
+ 85° C
+ 85° C
Active
Active
Active
Active
Active
Active
Active
Active
Rev. 1.33
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
XR88C92/192
Package Description
44 Pin LQFP Package
VCC
VCC
IP1
IP3
IP4
IP5
IP6
35
44
43
42
41
40
39
38
37
36
A3
IP0
-IOW
-IOR
RXB
TXB
OP1
OP3
OP5
OP7
N.C.
1
2
3
4
5
6
7
8
9
10
11
34
IP2
A2
A1
A0
33
32
31
30
29
-CS
RESET
XTAL2
XTAL1
RXA
TXA
OP0
OP2
OP4
OP6
N.C.
XR88C92
XR88C192
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
D2
GND
GND
-INT
D1
D3
D5
D7
D6
D4
Rev. 1.33
2
D0
22
XR88C92/192
Block Diagram
Channel A
Data Bus Buffers
&
Control Logic
Transmit
FIFO
Registers
Transmit
Shift
Register
TXA
D0-D7
-IOR
-IOW
RESET
Flow
Control
Logic
Receive
FIFO
Registers
Receive
Shift
Register
RXA
Watch
Dog
Timer
A0-A3
-CS
Register
Select
Logic
Flow
Control
Logic
Interconnect Bus Lines
&
Control Signals
Channel B
Transmit
FIFO
Registers
Transmit
Shift
Register
TXB
Interrupt
Control
Logic
Flow
Control
Logic
Receive
FIFO
Registers
Receive
Shift
Register
-INT
RXB
Watch
Dog
Timer
Flow
Control
Logic
XTAL1
XTAL2
Clock &
Baud Rate
Generator
OP0-OP7
Multi-
Purpose
I/O
Control
Logic
IP0-IP6
Rev. 1.33
3
XR88C92/192
SYMBOL DESCRIPTION
(* 44 pin LQFP)
Symbol
44
RXA, RXB
35,11
Pin
44*
29,5
Signal
type
I
Pin Description
Serial data input. The serial information (data) received from
serial port to XR88C92/192 receive input circuit. A mark (high)
is logic one and a space (low) is logic zero.This input must
be held at logic one when idle and during power down.
Serial data output. The serial data is transmitted via this pin
with additional start , stop and parity bits. This output will be
held in mark (high) state during reset, local loop back mode
or when the transmitter is disabled.
Master Reset (active high). A high on this pin will reset all the
outputs and internal registers. The transmitter output and
the receiver input will be disabled during reset time.
Multi-purpose output. General purpose output or Channel A
Request-To-Send (-RTSA active low).
Multi-purpose output. General purpose output or Channel B
Request-To-Send (-RTSB active low).
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bits 1,0;
TxAClk1
-Transmit 1X clock.
TxAClk16
-Transmit 16X clock
RxAClk1
-Receive 1X clock
TXA, TXB
33,13
28,6
O
RESET
38
32
I
OP0
32
27
O
OP1
14
7
O
OP2
31
26
O
OP3
15
8
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bits 3,2;
C/T
-Counter timer output (Open drain output)
TxBClk1
-Transmit 1X clock
RxBClk1
-Receive 1X clock
OP4
30
25
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bit 4;
-RxARDY -Receive ready signal (Open drain output)
-RxAFULL
- Receive FIFO full signal (Open drain output)
Rev. 1.33
4
XR88C92/192
SYMBOL DESCRIPTION
(* 44 pin LQFP)
Symbol
44
OP5
16
Pin
44*
9
Signal
type
O
Pin Description
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Confiuration Register bit 5;
-RxBRDY - Receive ready signal (Open drain output)
-RxBFULL
- Receive FIFO full signal (Open drain output)
OP6
29
24
O
Multi-purpose output. General purpose output or Transmit A
holding register empty interrupt (-TxARDY Open drain out-
put).
Multi-purpose output. General purpose output or Transmit B
holding register empty interrupt (-TxBRDY Open drain output)
OP7
17
10
O
A0-A3
2,4,
6,7
36
40,42,
44,1
30
I
I
Address select lines. To select internal registers.
Crystal input 1 or external clock input. A crystal can be
connected between this pin and XTAL2 pin to utilize the
internal oscillator circuit. An external clock can be used to
clock internal circuit and baud rate generator for custom
transmission rates.
Crystal input 2 or buffered clock output. See XTAL1.
Signal and power ground.
Interrupt output (open drain, active low) This pin goes low
upon occurrence of one or more of eight maskable interrupt
conditions (when enabled by the interrupt mask register).
CPU can read the interrupt status register to determine the
interrupting condition(s). This output requires a pull-up resis-
tor.
Multi-purpose input or Channel A Clear-To-Send (-CTSA
active low).
Multi-purpose input or Channel B Clear-To-Send (-CTSB
active low).
Multi-purpose input or Timer/Counter External clock input.
XTAL1
XTAL2
GND
-INT
37
22
24
31
16,17
18
O
Pwr
O
IP0
8
2
I
IP1
5
43
I
IP2
40
34
I
Rev. 1.33
5
