XRD9814B/XRD9816B
3-Channel 14/16-Bit Linear
CCD/CIS Sensor Signal Processors
November 2002-2
FEATURES
•
14-Bit (XRD9814B) or 16-Bit (XRD9816B)
A/D Converter
•
Triple-Channel, 2.5 MSPS Color Scan Mode
•
Single-Channel, 6 MSPS Monochrome Scan
Mode
•
Triple Correlated Double Sampler
•
Triple 10-Bit Programmable Gain Amplifier
•
Triple 10-Bit Offset Compensation DAC
•
Fully Differential or Single-Ended Inputs
•
CDS or S/H Mode
•
Inverting or Non-Inverting Mode
•
Internal Voltage Reference
•
Serial Control: On Data Bus or Separate Pins
•
Improved PGA Performance
GENERAL DESCRIPTION
The XRD9814B/9816B is a fully integrated, high-per-
formance analog signal processor/digitizer specifi-
cally designed for use in 3-channel linear Charge
Coupled Device (CCD) and Contact Image Sensitive
(CIS) imaging applications.
Each channel of the XRD9814B/9816B includes a
Correlated Double Sampler (CDS), Programmable
Gain Amplifier (PGA) and channel offset adjustment.
After gain and offset adjustment, the analog inputs are
sequentially sampled and digitized by an accurate 14/
16-bit A/D converter. The analog front-end can be
configured for inverting/non-inverting input, CDS or
sample-hold (S/H) mode, or AC/DC coupling,
making the XRD9814B/9816B suitable for use in CCD,
CIS and other data acquisition applications.
The CDS mode of operation supports both line and
pixel-clamp modes and can be used to achieve signifi-
cant reduction in system 1/f noise and CCD reset
clock feed-through. In S/H mode the internal DC-
restore voltage clamp can be enabled or disabled to
support AC-coupled or DC inputs. Sampling mode,
10-bit PGA gain (1024 linear steps), 8-bit fine offset
adjustment (256 linear steps), 2-bit gross offset adjust-
ment and input signal polarity are all programmable
through a serial interface. PGA gain range is 1 to 10,
and channel offset range is -300mV to 300mV for fine
adjustment and additional -400mV to +200mV for
gross offset adjustment. The A/D Full-Scale Range
(FSR) is programmable to 2V or 3V.
•
14-Bit or 8-Bit (Nibble) Parallel Data Output
(XRD9814B)
•
16-Bit or 8-Bit (Nibble) Parallel Data Output
(XRD9816B)
•
5V Operation and 3V I/O Compatibility
•
Low Power CMOS: 500mW @ 5V
APPLICATIONS
•
•
•
•
•
48-Bit Color Scanners (XRD9816B)
42-Bit Color Scanners (XRD9814B)
CCD or CIS Color Imagers
Gray Scale Scanners
Film Scanners
ORDERING INFORMATION
Part No.
XRD9814BCV
XRD9816BCV
Package Type
48-Lead TQFP
48-Lead TQFP
Temperature Range
0°C to +70°C
0°C to +70°C
Rev. 1.00
EXAR
Corporation, 48720 Kato Road, Fremont, CA 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRD9814B/9816B
BSAMP
VSAMP
ADCCLK
LCLMP
INTERNAL TIMING CONTROL
INSEL
10-BIT
RED(+)
RED(-)
PROGRAMMABLE
BUFFERED
CDS or S/H
PGA
I/O CONTROL AND
CONFIGURATION
REGISTERS
OUTSEL
SDI
SCLK
LOAD
REGISTER
AGND1
10-BIT
DAC
TEST1
TEST2
REGISTER
AVDD1
AVDD2
10-BIT
GRN(+)
GRN(-)
PROGRAMMABLE
BUFFERED
CDS or S/H
PGA
3-1
MUX
AVDD3
REGISTER
SGND
VREF
1.24V
OEB
AGND2
REGISTER
REFIN
OUTPUT
PORT
14/16-BIT A/D
10-BIT
BLU(+)
BLU(-)
PROGRAMMABLE
BUFFERED
CDS or S/H
PGA
CAPP
REGISTER
CAPN
VREF- VREF+
DB<13:0>
or
DB<15:0>
10-BIT
DAC
14/16
10-BIT
DAC
VCLAMP
(Internal)
CREF
DVDD
REGISTER
DGND
Figure 1. Block Diagram
Rev. 1.00
2
XRD9814B/9816B
OUTSEL
37
DGND
DVDD
LOAD
39
SCLK
PIN CONFIGURATION
DB10
DB11
DB12
DB13
DB9
48
47
46
45
44
43
42
41
40
38
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
N/C
N/C
AVDD3
OEB
SDI
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
INSEL
ADCCLK
BSAMP
VSAMP
LCLMP
AVDD1
AGND1
SGND
CAPN
CAPP
CREF
TEST2
XRD9814BCV
13
14
15
16
17
18
19
20
21
22
23
24
GRN(+)
RED(+)
AVDD2
AGND2
BLU(+)
GRN(-)
Note:
Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity
PIN DESCRIPTION - XRD9814B
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
N/C
N/C
AV
DD3
AV
DD2
AGND2
RED(+)
Description
Data Output Bit 8
Data Output Bit 7
Data Output Bit 6
Data Output Bit 5
Data Output Bit 4
Data Output Bit 3
Data Output Bit 2
Data Output Bit 1
Data Output Bit 0
No Connect
No Connect
Analog Power Supply
Analog Power Supply
Analog Ground (Substrate)
Red Positive Analog Input
Rev. 1.00
3
TEST1
N/C
N/C
RED(-)
BLU(-)
N/C
XRD9814B/9816B
PIN DESCRIPTION - XRD9814B (CONT'D)
Pin No.
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Name
RED(-)
N/C
GRN(+)
GRN(-)
N/C
BLU(+)
BLU(-)
N/C
TEST1
TEST2
CREF
CAPP
CAPN
SGND
AGND1
AV
DD1
LCLMP
VSAMP
BSAMP
ADCCLK
INSEL
OUTSEL
OEB
LOAD
SDI
SCLK
DGND
DV
DD
DB13
DB12
DB11
DB10
DB9
Description
Red Negative Analog Input
No Connect, (Note 5)
Green Positive Analog Input
Green Negative Analog Input
No Connect, (Note 5)
Blue Positive Analog Input
Blue Negative Analog Input
No Connect, (Note 5)
Internal Use Only
Internal Use Only
Decoupling Cap for CDS Reference
Decoupling Cap for Positive Reference
Decoupling Cap for Negative Reference
Substrate Gnd
Analog Ground (Substrate)
Analog Power Supply
Line Clamp Enable
Video Level Sampling Clock
Black Level Sampling Clock
A/D Converter Clock
Input Mode Select (Note 1)
Output Mode Select (Note 2)
Data Output Enable
Register Write Enable (Note 5)
Serial Data Input (Note 4)
Serial Shift Clock (Note 3)
Ground (Output Drivers and Internal Decode Logic)
Digital Power Supply (Output Drivers and Internal Decode Logic)
Data I/O Bit 13 (Note 4)
Data I/O Bit 12 (Note 3)
Data Output Bit 11
Data Output Bit 10
Data Output Bit 9
Note 1:
INSEL=0 —> SCLK, SDI, and LOAD pins are active for serial programming; INSEL=1 —> SCLK and SDI pins
are inactive, and the serial programming is done through I/O pins DB12 and DB13 as described in Notes 3~4 with
LOAD tri-stating DB12 and DB13.
Note 2:
OUTSEL=0 —> 14-bit parallel output mode select; OUTSEL=1 —> 8-bit nibble output mode select.
Note 3:
For INSEL=1, DB12 becomes the SCLK input during serial programming.
Note 4:
For INSEL=1, DB13 becomes the SDI input during serial programming.
Note 5:
Pins 17, 20 and 23 may be connected to AGND2 to improve noise immunity.
Rev. 1.00
4
XRD9814B/9816B
OUTSEL
37
DGND
PIN CONFIGURATION
DVDD
DB11
DB12
DB13
DB14
DB15
LOAD
39
SCLK
48
47
46
45
44
43
42
41
40
38
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AVDD3
OEB
SDI
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
INSEL
ADCCLK
BSAMP
VSAMP
LCLMP
AVDD1
AGND1
SGND
CAPN
CAPP
CREF
TEST2
XRD9816BCV
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
RED(+)
GRN(+)
AVDD2
AGND2
BLU(+)
GRN(-)
Note:
Pins 17,20 and 23 should be connected to AGND2 to improve noise immunity
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Name
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
AV
DD3
AV
DD2
AGND2
RED(+)
Description
Data Output Bit 10
Data Output Bit9
Data Output Bit 8
Data Output Bit 7
Data Output Bit 6
Data Output Bit 5
Data Output Bit 4
Data Output Bit 3
Data Output Bit 2
Data Output Bit 1
Data Output Bit 0
Analog Power Supply
Analog Power Supply
Analog Ground (Substrate)
Red Positive Analog Input
Rev. 1.00
5
TEST1
N/C
N/C
RED(-)
BLU(-)
N/C
