xr
JULY 2004
XRT83D10
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
GENERAL DESCRIPTION
The XRT83D10 is a fully integrated, single channel,
Line Interface Unit (Transceiver) for 75
Ω
or 120
Ω
E1
(2.048 Mbps) and 100Ω DS1 (1.544 Mbps)
applications. The LIU consists of a receiver with
adaptive data slicer for accurate data and clock
recovery and a transmitter which accepts dual-rail
digital inputs for signal transmission to the line using
a low- impedance differential line driver. The LIU also
includes a crystal-less jitter attenuator for clock and
data smoothing which, depending on system
requirements, can be selected in either the transmit
or receive path.
The XRT83D10 uses the transformer coupling on
both the Receiver and Transmitter sides, and
supports both 120Ω balanced,75Ω unbalanced and
100Ω
interfaces.
FEATURES
•
Complete E1 (CEPT) and DS1 Line Interface Unit
•
Generates transmit output pulses that are compli-
ant with the ITU-T G.703 Pulse Template for
2.048Mbps (E1) rates
F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT83D10
•
On-Chip Pulse Shaping for both 75
Ω
,120
Ω
and
100
Ω
Line Drivers
•
Clock Recovery and Selectable Crystal-less Jitter
attenuator
•
Compliant with ETS300166 Return Loss
•
Compliant with the ITU-T G.823 Jitter Tolerance
Requirements
•
Remote, Local and Digital Loop backs
•
Declares and Clears LOS per ITU-T G.775
•
-
40°
C to
85°
C Temperature Range
•
Low
Power Dissipation
•
+5V or +3.3V Supply Operation
•
Pin Compatible with AGERE T7290A and T5290A
APPLICATIONS
•
PDH Multiplexers
•
SDH Multiplexers
•
Digital Cross-Connect Systems
•
DECT (Digital European Cordless Telephone) Base
Stations
•
CSU/DSU Equipment
R LO S
A LO S
R TIP
R eceive
D ata
D LO S
R R IN G
P ea k
D ete ctor
D a ta
S lice r
D LO S
D ata &
Tim in g
R e co very
2
MODE1
MODE2
2
Loca l
L oop ba ck
LP1
2
D igital
Lo opb ack
LP 3
2
R PD AT A
RNDATA
R C LK
FOFS
E XC LK
Tim in g
G en erato r
Jitter
A tten uato r
2
S C LK
T TIP
T ransm it
D ata
T x Line
D river
P ulse
E qu alizer
2
2
2
2
T R IN G
R e m o te
Loo back
LP2
E XC LK
TAOS
EC1
EC2
EC3
M O D E1
M O D E2
TPDATA
TNDATA
T C LK
E X C LK
TAOS
EC1
EC2
EC3
M O D E1
M O D E2
LO O P A
LO O P B
CS
V
DDA
, G N D
A
V
DDD
, G N D
D
+
Transm it
M o nitor
TSC
Loss o f
C lo ck
TA O S
TA O S
MODE2
E XC LK
IC T
C LK LO S
JA
C lock
Local
R em ote
D igital
µP
Inte rface
D ecod e
4
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT83D10
REV. 1.0.3
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
xr
PRODUCT ORDERING INFORMATION
P
RODUCT
N
UMBER
XRT83D10IW
P
ACKAGE
T
YPE
28 Lead 300 Mil Jedec SOJ
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
F
IGURE
2. P
IN
O
UT OF THE
XRT83D10
EC1
ICT
AVDD
AGND
RRING
RTIP
MODE2
MODE1
LOOPB
LOOPA
TAOS
RLOS
FOFS
CLKLOS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
EC2
EC3
DGND
TRING
DVDD
TTIP
RNDATA
RPDATA
RCLK
TNDATA
TPDATA
TCLK
EXCLK
CS
17
16
15
2
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
xr
XRT83D10
REV. 1.0.3
PIN DESCRIPTIONS
MICROPROCESSOR
P
IN
#
15
N
AME
CS
T
YPE
I
D
ESCRIPTION
Microprocessor Interface Select (Active Low)
CS loads the data into the device on its falling edge and latches the data on its
rising edge.
For Hardware mode, CS is left open or connected to GND.
N
OTE
:
Internally pulled down
1
EC1
I
Transmit Equalization Control.
The three inputs, EC1,EC2 and EC3 are used for selecting transmit equaliza-
tion.
N
OTE
:
Internally Pulled down.
27
EC3
I
Transmit Equalization Control
N
OTE
:
Internally Pulled down.
28
EC2
I
Transmit Equalization Control
N
OTE
:
Internally Pulled down.
7
MODE2
I
Mode Select
Mode 1 and Mode 2 select the clock and data paths through the jitter attenua-
tor.
N
OTE
:
Internally Pulled down.
8
MODE1
I
Mode Select
N
OTE
:
Internally Pulled down.
9
LOOPB
I
Loopback control.
LOOPB along with LOOPA are used for selecting different loopbacks.
LOOPA
0
0
1
1
N
OTE
:
Internally Pulled down.
10
LOOPA
I
LOOPB
0
1
0
1
Loopback Mode
Normal Operation
Digital
Remote
Local
Loopback control.
LOOPB along with LOOPA are used for selecting different loopbacks.
N
OTE
:
Internally Pulled down.
3
XRT83D10
REV. 1.0.3
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
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RECEIVER SECTION
P
IN
#
6
5
20
N
AME
RTIP
RRING
RCLK
T
YPE
I
I
O
D
ESCRIPTION
Receive positive bipolar data Input
Receive negative bipolar data Input
Receive Clock Output
Recovered receive clock for the terminal equipment.
Receive positive NRZ data:
Recovered positive data DS1 (1.544Mbits/s) or CEPT (2.048 Mbits/s)
Receive negative data
Recovered negative NRZ data DS1 (1.544Mbits/s) or CEPT (2.048 Mbits/s)
Receive Loss of Signal:
This pin is set "High" if analog loss-of-signal at the receiver input is detected or
if digital loss-of-signal of the recovered data is detected.RLOS will remain
"High" until the loss of signal condition clears.
21
RPDATA
O
22
RNDATA
O
12
RLOS
O
TRANSMITTER SECTION
P
IN
#
17
N
AME
TCLK
T
YPE
I
D
ESCRIPTION
Transmit Clock
DS1 Clock Signal. (1.544 MHz ± 130 ppm) or CEPT clock signal (2.048 MHz ±
80 ppm).
Transmit Positive Data
DS1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) positive bipolar data
Transmit Negative Data
DS1 (1.544 Mbits/s) or CEPT (2.048 Mbits/s) negative bipolar data
Transmit Tip Output
Positive bipolar transmit data
Transmit Differential Ring Output
Negative bipolar transmit data
Loss of Clock Signal:
This pin is set "High" when either the transmit clock (TCLK) or the clock output
from the jitter attenuator is absent.
18
19
23
25
14
TPDATA
TNDATA
TTIP
TRING
CLKLOS
I
I
O
O
O
4
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
xr
XRT83D10
REV. 1.0.3
CONTROL FUNCTION
P
IN
#
2
N
AME
ICT
T
YPE
I
D
ESCRIPTION
In Circuit Testing
When this pin is tied "Low" all output pins are forced to high-impedance state
for in-circuit testing.
N
OTE
:
Internally pulled up.
16
ExCLK
I
External Clock Input:
DS1 (1.544 MHz ± 130 ppm) or CEPT E1 (2.048 MHz ± 80 ppm) clock signal is
provided. ExCLK must be an independent clock to guarantee device perfor-
mance for all specifications. This clock must be continuously active (ungapped
or unswitched) and void of jitter for the device to operate properly.
Transmit All Ones:
With this pin tied "High", an AMI encoded all "1’s" signal sent to the transmit
output using ExCLK as the timing reference. A remote loop back has higher
priority over TAOS request.
N
OTE
:
Internally pulled down.
11
TAOS
I
9
LOOPB
I
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
LOOPA
0
0
1
1
N
OTE
:
Internally Pulled down.
10
LOOPA
I
LOOPB
0
1
0
1
Loopback Mode
Normal Operation
Digital
Remote
Local
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
N
OTE
:
Internally Pulled down.
13
FOFS
O
FIFO Overflow Signal:
This pin is set "High" if the phase jitter of the incoming signal exceeds the toler-
ance of the jitter attenuator’s buffer. This may result in loss of data and Jitter
Attenuator is no longer attenuating jitter.
POWER AND GROUND
P
IN
#
3
4
24
26
N
AME
AVDD
AGND
DVDD
DGND
T
YPE
****
****
****
****
D
ESCRIPTION
Analog Supply: 5V ± 5% or 3.3V ± 5%
Analog GND.
Digital Supply: 5V ± 5% or 3.3V ± 5%
Digital GND
5
