XRT84L38
OCTAL T1/E1/J1 FRAMER
SEPTEMBER 2006
REV. 1.0.1
GENERAL DESCRIPTION
The XRT84L38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framing controller. The
XRT84L38 contains an integrated DS1/E1/J1 framer
which provides DS1/E1/J1 framing and error
accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers, and
can be independently enabled or disabled as
required and can be configured to frame to the
common DS1/E1/J1 signal formats
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function including 3 HDLC
controllers to support V5.2. Each Transmit HDLC
controller encapsulates contents of the Transmit
HDLC buffers into LAPD Message frames. Each
Receive HDLC controller extracts payload content of
Receive LAPD Message frames from the incoming
T1/E1/J1 data stream and writes it into the Receive
HDLC buffer. Each framer also contains a Transmit
and Overhead Data Input port, which permits Data
Link Terminal Equipment direct access to the
outbound T1/E1/J1 frames Likewise, a Receive
Overhead output data port permits Data Link Terminal
Equipment direct access to the Data Link bits of the
inbound T1/E1/J1 frames.
The XRT84L38 fully meets all of the latest T1/E1/J1
specifications:
ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
F
IGURE
1. XRT84L38 8-
CHANNEL
DS1 (T1/E1/J1) F
RAMER
External Data
Link Controller
Local PCM
Highway
XRT84L38
1 of 8-channels
8
Tx Overhead In
Rx Overhead Out
TxPOS
8
TxNEG
8
TxLineCLK 8
8 DS1/E1
Channels
1.544/2.048 MHz
XRT83L38
TPOS
TNEG
TCLK1
Tx Serial
Data In
2-Frame
Slip Buffer
Elastic Store
Tx Framer
Tx Encoder
LIU
Interface
LLB
LB
Tx1
Twisted
Pair
Tx Serial
Clock
Rx1
RxPOS
8
RxNEG
8
RxLineCLK 8
RPOS
RNEG
RCLK1
µP
Interface
Tx8
ST-BUS
Twisted
Pair
8
Rx Serial
Data Out
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Rx Encoder
LIU
Interface
LIU &
Loopback
Control
Rx Serial
Clock
PRBS
Generator &
Analyser
Performance
Monitor
HDLC (LAPD)
Controller &
96-byte Buffer
8kHz sync
OSC
Signaling &
Alarms
JTAG
DMA
Interface
Rx8
Microprocessor
Interface
Back Plane
1.544-16.384 Mbit/s
8-CH T1/E1/LIU
Host Mode
Interrupt
D[7:0]
A[6:0]
4 WR
ALE_AS
Channel
RD
Select
RDY_DTACK
3
System (Terminal) Side
Memory
Intel/Motorola µP
Configuration, Control &
Status Monitor
Line Side
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT84L38
OCTAL T1/E1/J1 FRAMER
APPLICATIONS
REV. 1.0.1
•
High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems
•
SONET/SDH terminal or Add/Drop multiplexers (ADMs)
•
T1/E1/J1 add/drop multiplexers (MUX)
•
Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1
•
Digital Access Cross-connect System (DACs)
•
Digital Cross-connect Systems (DCS)
•
Frame Relay Switches and Access Devices (FRADS)
•
ISDN Primary Rate Interfaces (PRA)
•
PBXs and PCM channel bank
•
T3 channelized access concentrators and M13 MUX
•
Wireless base stations
•
ATM equipment with integrated DS1 interfaces
•
Multichannel DS1 Test Equipment
•
T1/E1/J1 Performance Monitoring
•
Voice over packet gateways
•
Routers
FEATURES
•
Eight independent, full duplex DS1 Tx and Rx Framers
•
Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
•
Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
•
Programmable output clocks for Fractional T1/E1/J1
•
Supports Channel Associated Signaling (CAS)
•
Supports Common Channel Signalling (CCS)
•
Supports ISDN Primary Rate Interface (ISDN PRI) signaling
•
Extracts and inserts robbed bit signaling (RBS)
•
3 independent HDLC Controllers for Receive and Transmit on a per channel basis
•
Each HDLC controller contains two 96-BYTE buffers
•
Timeslot assignable HDLC
•
V5.1 and V5.2 Interface
•
8-bit Intel/Motorola
μP
and MIPS Power PC interfaces for configuration, control and status monitoring
•
Parallel search algorithm for fast frame synchronization
•
Wide choice of T1 framing structures: D4, ESF, SLC®96, TIDM and N-Frame (non-framing)
•
Direct access to D and E channels for fast transmission of data link information
•
PRBS and QRSS generation and detection
2
XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
•
Programmable Interrupt output pin
•
Supports programmed I/O, Burst and DMA modes of Read-Write access
•
Each framer block encodes and decodes the T1/E1/J1 Frame serial data into and from the Single-rail or
Dual-rail (B8ZS) format
•
Dual or single rail line side digital PCM inputs
•
Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms
•
Detects OOF, LOF, LOS errors and COFA conditions
•
Loopbacks: Local (LLB) and Line remote (LB)
•
Facilitates Inverse Multiplexing for ATM
•
Performance monitor with one second polling
•
Boundary scan (IEEE 1149.1) JTAG test port
•
Accepts external 8kHz Sync reference
•
3.3V CMOS operation with 5V tolerant inputs
•
388-pin BGA package with –40°C to +85°C operation
•
Direct Interface to Exar’s XRT83L38 (Octal) LIU
ORDERING INFORMATION
P
ART
N
UMBER
XRT84L38IB
P
ACKAGE
388 Pin Plastic Ball Grid Array
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
3
XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
F
IGURE
2. P
IN
O
UT OF THE
XRT84L38 T
OP
V
IEW
(
SEE PIN LIST FOR NAMES AND FUNCTION
)
(See pin list for pin names and function)
Top View
A1
B1
C1
D4
E1
F1
G1
H1
J1
K1
L1
M1
N1
P1
R1
T1
U1
V1
W1
Y1
AA
1
AB
1
AC
1
AD
1
AE
1
AF
1
AC
4
AC
23
T2
T3
T4
L2
L3
L4
V3
V1
V1
V1
V1
G
V3
V1
V1
V1
V1
G
V3
G
G
G
G
G
V3
G
G
G
G
G
V3
V2
V2
V2
V2
G
V3
V2
V2
V2
V2
G
T
23
T
24
T
25
L
23
L
24
L
25
D4
D
23
A
26
AF
AE
AD
D
26
AC
AB
AA
Y
W
V
U
L
26
T
R
P
N
M
T
26
L
K
J
H
G
F
E
XRT84L38
AC
26
D
C
B
AF
26
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
4
XRT84L38
REV. 1.0.1
OCTAL T1/E1/J1 FRAMER
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................ 1
F
IGURE
1. XRT84L38 8-
CHANNEL
DS1 (T1/E1/J1) F
RAMER
............................................................................................................ 1
A
PPLICATIONS
.............................................................................................................................................. 2
F
EATURES
.................................................................................................................................................... 2
ORDERING INFORMATION ................................................................................................................... 3
F
IGURE
2. P
IN
O
UT
T
ABLE
1: L
IST
BY
OF THE
XRT84L38 T
OP
V
IEW
(
SEE PIN
LIST FOR NAMES AND FUNCTION
) ............................................................
4
TABLE OF CONTENTS .....................................................................................................
I
P
IN
N
UMBER
......................................................................................................................................................... 5
PIN DESCRIPTIONS ......................................................................................................... 5
T
RANSMIT
S
ERIAL
D
ATA
I
NPUT
...................................................................................................................... 5
O
VERHEAD
I
NTERFACE
............................................................................................................................... 14
R
ECEIVE
S
ERIAL
D
ATA
O
UTPUT
.................................................................................................................. 16
R
ECEIVE
D
ECODER
L
IU
I
NTERFACE
............................................................................................................. 23
T
RANSMIT
E
NCODER
L
IU
I
NTERFACE
........................................................................................................... 23
T
IMING
....................................................................................................................................................... 24
L
IU
C
ONTROL
............................................................................................................................................. 25
JTAG......................................................................................................................................................... 26
M
ICROPROCESSOR
I
NTERFACE
.................................................................................................................... 27
P
OWER
S
UPPLY
P
INS
................................................................................................................................. 30
G
ROUND
P
INS
............................................................................................................................................ 30
N
O
C
ONNECT
P
INS
..................................................................................................................................... 31
E
LECTRICAL
C
HARACTERISTICS
................................................................................................................... 32
A
BSOLUTE
M
AXIMUMS
................................................................................................................................ 32
DC E
LECTRICAL
C
HARACTERISTICS
............................................................................................................. 32
T
ABLE
2: XRT84L38 P
OWER
C
ONSUMPTION
................................................................................................................................. 32
1.0 MICROPROCESSOR INTERFACE BLOCK ......................................................................................... 33
T
ABLE
3: µC/µP S
ELECTION
T
ABLE
................................................................................................................................................ 33
1.1 CHANNEL SELECTION WITHIN THE FRAMER .............................................................................................. 34
T
ABLE
4: C
HANNEL
S
ELECTION
...................................................................................................................................................... 34
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM OF THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
.................................................................... 35
1.2 THE MICROPROCESSOR INTERFACE BLOCK SIGNAL .............................................................................. 35
T
ABLE
5: XRT84L38 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH THE
I
NTEL AND
M
OTOROLA
M
ODES
35
T
ABLE
6: I
NTEL MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
...................................................................................................... 36
T
ABLE
7: M
OTOROLA
M
ODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
............................................................................................. 36
1.3 INTERFACING THE XRT84L38 TO THE LOCAL µC/µP VIA THE MICROPROCESSOR INTERFACE BLOCK 36
1.3.1 INTERFACING THE FRAMER TO THE MICROPROCESSOR OVER AN 8 BIT WIDE BI-DIRECTIONAL DATA BUS 37
1.3.2 DATA ACCESS MODES............................................................................................................................................... 37
1.3.2.1 P
ROGRAMMED
I/O ................................................................................................................................................ 37
1.3.2.2 D
ATA
A
CCESS USING
P
ROGRAMMED
I/O ............................................................................................................... 37
F
IGURE
4. I
NTEL
µP I
NTERFACE SIGNALS DURING
P
ROGRAMMED
I/O R
EAD
O
PERATION
................................................................... 38
F
IGURE
5. I
NTEL
µP I
NTERFACE
S
IGNALS DURING
P
ROGRAMMED
I/O W
RITE
O
PERATION
................................................................. 39
F
IGURE
6. M
OTOROLA
µP I
NTERFACE SIGNALS DURING A
P
ROGRAMMED
I/O R
EAD
O
PERATION
....................................................... 40
F
IGURE
7. M
OTOROLA
µP I
NTERFACE SIGNAL DURING
P
ROGRAMMED
I/O W
RITE
O
PERATION
........................................................... 41
1.3.2.3 B
URST
M
ODE
I/O
FOR
D
ATA
A
CCESS
................................................................................................................... 41
F
IGURE
8. I
NTEL
µP I
NTERFACE
S
IGNALS
,
DURING THE
I
NITIAL
R
EAD
O
PERATION OF A
B
URST
C
YCLE
.............................................. 43
F
IGURE
9. I
NTEL
µP I
NTERFACE
S
IGNALS
,
DURING SUBSEQUENT
R
EAD
O
PERATIONS OF A
B
URST
I/O C
YCLE
................................... 44
F
IGURE
10. I
NTEL
µP I
NTERFACE SIGNALS
,
DURING THE
I
NITIAL
W
RITE
O
PERATION OF A
B
URST
C
YCLE
........................................... 46
F
IGURE
11. µP I
NTERFACE
S
IGNALS
,
DURING SUBSEQUENT
W
RITE
O
PERATIONS OF A
B
URST
I/O C
YCLE
......................................... 47
F
IGURE
12. M
OTOROLA
µP I
NTERFACE
S
IGNALS DURING THE
I
NITIAL
R
EAD
O
PERATION OF A
B
URST
C
YCLE
.................................... 48
F
IGURE
13. M
OTOROLA
µP I
NTERFACE
S
IGNALS
,
DURING SUBSEQUENT
R
EAD
O
PERATIONS OF A
B
URST
I/O C
YCLE
........................ 49
F
IGURE
14. M
OTOROLA
µP I
NTERFACE SIGNALS
,
DURING THE
I
NITIAL
W
RITE
O
PERATION OF A
B
URST
C
YCLE
.................................. 51
F
IGURE
15. M
OTOROLA
µP I
NTERFACE
S
IGNALS DURING SUBSEQUENT
W
RITE
O
PERATIONS OF A
B
URST
I/O C
YCLE
........................ 52
1.4 DMA READ/WRITE OPERATIONS................................................................................................................... 52
DMA-0 Write DMA Interface ..................................................................................................................................... 53
F
IGURE
16. DMA M
ODE FOR THE
XRT84L38
AND
A
M
ICROPROCESSOR
......................................................................................... 53
1.5 MEMORY AND REGISTER MAP ...................................................................................................................... 53
1.5.1 MEMORY MAPPED I/O INDIRECT ADDRESSING...................................................................................................... 53
I
测试/测量
