XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
JULY 2008
REV. 1.0.2
GENERAL DESCRIPTION
The XRT91L31 is a fully integrated SONET/SDH
transceiver for SONET/SDH 622.08 Mbps STS-12/
STM-4 or 155.52 Mbps STS-3/STM-1 applications.
The transceiver includes an on-chip Clock Multiplier
Unit (CMU), which uses a high frequency Phase-
Locked Loop (PLL) to generate the high-speed
transmit serial clock from a slower external clock
reference. It also provides Clock and Data Recovery
(CDR) function by synchronizing its on-chip Voltage
Controlled Oscillator (VCO) to the incoming serial
data stream. The internal CDR unit can be disabled
and bypassed in lieu of an externally recovered
received clock from the optical module. Either the
internally recovered clock or the externally recovered
clock can be used for loop timing applications. The
chip provides serial-to-parallel and parallel-to-serial
converters using an 8-bit wide LVTTL system
interface in both receive and transmit directions.
The transmit section includes an option to accept a
parallel clock signal from the framer/mapper to
F
IGURE
1. B
LOCK
D
IAGRAM OF
XRT91L31
synchronize the transmit section timing. The device
can internally monitor Loss of Signal (LOS) condition
and automatically mute received data upon LOS. An
on-chip SONET/SDH frame byte and boundary
detector and frame pulse generator offers the ability
recover SONET/SDH framing and to byte align the
receive serial data stream into the 8-bit parallel bus.
APPLICATIONS
•
SONET/SDH-based Transmission Systems
•
Add/Drop Multiplexers
•
Cross Connect Equipment
•
ATM and Multi-Service Switches, Routers and
Switch/Routers
•
DSLAMS
•
SONET/SDH Test Equipment
•
DWDM Termination Equipment
STS-12/STM-4 or STS-3/STM-1
TRANSCEIVER
TXDI[7:0]
8
TXPCLK_IO
REFCLKP/N
TTLREFCLK
PISO
(Parallel Input
Serial Output)
ENB
Re-Timer
TXOP/N
MUX
Div by
8
ENB
XOR
CMU
DLOOP
RLOOPS
ALOOP
MUX
CDRAUXREFCLK
MUX
RXDO[7:0]
SIPO
(Serial Input
Parallel Output)
CDR
MUX
RXIP/N
8
XRXCLKIP/N
RXPCLKO
Div by 8
Control Block
Loop Filters
Clock Control
CAP1P
CAP2P
CAP1N
CAP2N
DLOSDIS
LOSEXT
OOF
FRAMEPULSE
CDRDIS
CMUFREQSEL
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
STS-12/STS-3
CDRREFSEL
LOOPTIME
PIO_CTRL
RLOOPS
DLOOP
ALOOP
Reset
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
FEATURES
REV. 1.0.2
•
Targeted for SONET STS-12/STS-3 and SDH STM-4/STM-1 Applications
•
Selectable full duplex operation between STS-12/STM-4 standard rate of 622.08 Mbps or STS-3/STM-1
155.52 Mbps
•
Single-chip fully integrated solution containing parallel-to-serial converter, clock multiplier unit (CMU), serial-
to-parallel converter, clock data recovery (CDR) functions, and a SONET/SDH frame and byte boundary
detection circuit
•
Ability to disable and bypass onchip CDR for external based received reference clock recovery thru
Differential LVPECL input pins XRXCLKIP/N
•
8-bit LVTTL parallel data bus paths running at 77.76 Mbps in STS-12/STM-4 or 19.44 Mbps in STS-3/STM-1
mode of operation
•
Uses Differential LVPECL or Single-Ended LVTTL CMU reference clock frequencies of either 19.44 MHz or
77.76 MHz for both STS-12/STM-1 or STS-3/STM-1 operations
•
Optional use of 77.76 MHz Single-Ended LVTTL input for independent CDR reference clock operation
•
Able to Detect and Recover SONET/SDH frame boundary and byte align received data on the parallel bus
•
Diagnostics features include LOS monitoring and automatic received data mute upon LOS
•
Provides Local, Remote and Split Loop-Back modes as well as Loop Timing mode
•
Optional flexibility to re-configure the transmit parallel bus clock output to a clock input and accept timing
signal from the framer/mapper device to permit the framer/mapper device time domain to be synchronized
with the transceiver transmit timing.
•
Meets Telcordia, ANSI and ITU-T G.783 and G.825 SDH jitter requirements including T1.105.03 - 2002
SONET Jitter Tolerance specification, Bellcore TR-NWT-000253 and GR-253-CORE, GR-253 ILR SONET
Jitter specifications.
•
Complies with ANSI/TIA/EIA-644 and IEEE P1596.3 3.3V LVDS standard, 3.3V LVPECL, and JESD 8-B
LVTTL and LVCMOS standard.
•
Operates at 3.3V with 3.3V I/O
•
Less than 660mW in STS-3/STM-1 mode or 800mW in STS-12/STM-4 mode Typical Power Dissipation
•
Package: 10 x 10 x 2.0 mm 64-pin QFP
2
XRT91L31
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
F
IGURE
2. 64 QFP P
IN
O
UT OF THE
XRT91L31 (T
OP
V
IEW
)
AVDD
PIO_CTRL
GND
VDD3.3
RRCLK_1
GND
RRPOS_1
GND
RRNEG_1
AGND_RX
RCLKES
AVDD3.3_RX
NC
CAP2P
VDD
CAP2N
DS3/E3_2
CAP1N
SDO
CAP1P
FSS
AVDD3.3_TX
RRNEG_2
AGND_TX
RRPOS_2
TTLREFCLK
RRCLK_2
GND
GND
VDD3.3
AVDD
LOSEXT
49
50
49
51
50
52
51
53
52
54
53
55
54
56
55
57
56
58
57
59
58
60
59
61
60
61
62
62
63
63
64
64
48
48
47
47
46
46
45
45
44
44
43
43
42
42
41
41
40
40
39
39
38
38
37
37
36
36
35
35
34
34
33
33
32
31
32
30
31
29
30
28
29
27
28
26
27
25
26
24
25
23
24
22
23
21
22
20
21
19
20
18
19
17
18
17
P
ART
N
UMBER
XRT91L31IQ
RESET
RESET
LOOPTM_NOJA
LOOPTIME
CMUFREQSEL
CMUFREQSEL
VDD_PECL
VDD_PECL
TXOP
TXOP
TXON
TXON
LOSDDIS
DLOSDIS
EXTRXCLKIP
XRXCLKIP
EXTRXCLKIN
XRXCLKIN
VDD_PECL
VDD_PECL
OOF
OOF
CDRDIS
CDRDIS
RXIP
RXIP
RXIN
RXIN
VDD3.3
VDD/CDR_BW
REFCLKP
REFCLKP
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
AGND
TXPCLK_IO
FL1
TXDI7
STS1_1
TXDI6
MCLK_1
GND
GND
TXDI5
RCLK_1
TXDI4
RPOS_1
TXDI3
RNEG_1
TXDI2
VDD
TXDI1
RNEG_0
TXDI0
RPOS_0
STS12/STS3
RCLK_0
CDRREFSEL
GND
VDD3.3
MCLK_0
DLOOP
DJA_1/SDI
RLOOPS
AGND
ALOOP
XRT91L30
XRT91L31
AGND
FL_2
CDRAUXREFCLK
STS1_2
VDD3.3
DJA_2/CS
FRAMEPULSE
MCLK_2
RXPCLKO
GND
GND
RXDO7
RCLK_2
RXDO6
VDD
RXDO5
RNEG_2
RXDO4
RPOS_2
RXDO3
GND
RXDO2
DJA_0/SCLK
GND
DS3/E3_0
RXDO1
STS1_0
RXDO0
FL0
VDD3.3
AGND
REFCLKN
T
ABLE
1: O
RDERING
I
NFORMATION
P
ACKAGE
64 Pin Lead QFP
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
3
XRT91L31
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
REV. 1.0.2
GENERAL DESCRIPTION .................................................................................................1
APPLICATIONS ...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM OF
XRT91L31 ...................................................................................................................................... 1
FEATURES
......................................................................................................................................................2
F
IGURE
2. 64 QFP P
IN
O
UT OF THE
XRT91L31 (T
OP
V
IEW
)............................................................................................................ 3
T
ABLE
1: O
RDERING
I
NFORMATION
................................................................................................................................................... 3
PIN DESCRIPTIONS ..........................................................................................................6
.....................................................................................................................................................................6
T
ABLE
2: H
ARDWARE
C
ONTROL
....................................................................................................................................................... 6
T
RANSMITTER
S
ECTION
..................................................................................................................................9
R
ECEIVER
S
ECTION
......................................................................................................................................11
P
OWER AND
G
ROUND
..................................................................................................................................12
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................14
1.1 STS-12/STM-4 AND STS-3/STM-1 MODE OF OPERATION ......................................................................... 14
1.2 CLOCK INPUT REFERENCE FOR CLOCK MULTIPLIER (SYNTHESIZER) UNIT ...................................... 14
T
ABLE
3: CMU R
EFERENCE
F
REQUENCY
O
PTIONS
(D
IFFERENTIAL OR
S
INGLE
-E
NDED
) ................................................................... 14
1.3 DATA LATENCY ............................................................................................................................................. 14
T
ABLE
4: D
ATA INGRESS TO DATA EGRESS LATENCY
....................................................................................................................... 14
2.0 RECEIVE SECTION .............................................................................................................................15
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 15
F
IGURE
3. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 15
2.2 RECIEVE SERIAL DATA INPUT TIMING ...................................................................................................... 16
F
IGURE
4. R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
D
IAGRAM
.......................................................................................... 16
T
ABLE
5: R
ECEIVE
H
IGH
-
SPEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ............................................................. 16
T
ABLE
6: R
ECEIVE
H
IGH
-S
PEED
S
ERIAL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
) ............................................................... 16
...................................................................................................................................................................16
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 17
T
ABLE
7: C
LOCK
D
ATA
R
ECOVERY UNIT REFERENCE CLOCK SETTINGS
............................................................................................ 17
T
ABLE
8: CDR AUXREFCLK R
EFERENCE
F
REQUENCY
R
EQUIREMENT
F
OR
C
LOCK AND
D
ATA
R
ECOVERY
..................................... 17
2.3.1 INTERNAL CLOCK AND DATA RECOVERY BYPASS ............................................................................................ 17
F
IGURE
5. I
NTERNAL
C
LOCK AND
D
ATA
R
ECOVERY
B
YPASS
............................................................................................................ 18
2.4 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 19
F
IGURE
6. E
XTERNAL
L
OOP
F
ILTERS
.............................................................................................................................................. 19
2.5 LOSS OF SIGNAL .......................................................................................................................................... 19
F
IGURE
7. LOS D
ECLARATION
C
IRCUIT
.......................................................................................................................................... 19
2.6 SONET FRAME BOUNDARY DETECTION AND BYTE ALIGNMENT RECOVERY .................................... 20
2.7 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 20
F
IGURE
8. S
IMPLIFIED
B
LOCK
D
IAGRAM OF
SIPO ........................................................................................................................... 20
2.8 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 21
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 21
2.9 DISABLE PARALLEL RECEIVE DATA OUTPUT UPON LOS ..................................................................... 21
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 22
F
IGURE
10. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
............................................................................................................................ 22
T
ABLE
9: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ......................................................................... 22
T
ABLE
10: R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
T
IMING
(STS-3/STM-1 O
PERATION
) ......................................................................... 22
T
ABLE
11: PECL
AND
TTL R
ECEIVE
O
UTPUTS
T
IMING
S
PECIFICATION
............................................................................................ 23
3.0 TRANSMIT SECTION ..........................................................................................................................24
3.1 TRANSMIT PARALLEL INPUT INTERFACE ................................................................................................. 24
F
IGURE
11. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................. 24
3.2 TRANSMIT PARALLEL DATA INPUT TIMING .............................................................................................. 25
F
IGURE
12. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 25
T
ABLE
12: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
)......................................................................... 25
...................................................................................................................................................................25
T
ABLE
13: T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
)........................................................................... 25
...................................................................................................................................................................25
3.3 ALTERNATE TRANSMIT PARALLEL BUS CLOCK INPUT OPTION .......................................................... 26
F
IGURE
13. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
(P
ARALLEL
C
LOCK
I
NPUT
O
PTION
) ...................................... 26
3.4 ALTERNATE TRANSMIT PARALLEL DATA INPUT TIMING ....................................................................... 26
F
IGURE
14. A
LTERNATE
T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
............................................................................................................ 26
T
ABLE
14: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-12/STM-4 O
PERATION
) ...................................................... 27
...................................................................................................................................................................27
4
XRT91L31
REV. 1.0.2
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
T
ABLE
15: A
LTERNATE
T
RANSMIT
P
ARALLEL
D
ATA
I
NPUT
T
IMING
(STS-3/STM-1 O
PERATION
). ....................................................... 27
................................................................................................................................................................... 27
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 27
F
IGURE
15. S
IMPLIFIED
B
LOCK
D
IAGRAM OF
PISO ......................................................................................................................... 27
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 28
T
ABLE
16: C
LOCK
M
ULTIPLIER
U
NIT REQUIREMENTS FOR REFERENCE CLOCK
.................................................................................. 28
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 29
T
ABLE
17: L
OOP
T
IMING AND
C
LOCK
R
ECOVERY CONFIGURATIONS
................................................................................................. 29
F
IGURE
16. L
OOP
T
IMING
M
ODE
U
SING
I
NTERNAL
CDR
OR AN
E
XTERNAL
R
ECOVERED
C
LOCK
....................................................... 30
3.8 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 30
F
IGURE
17. T
RANSMIT
S
ERIAL
O
UTPUT
I
NTERFACE BLOCK
.............................................................................................................. 30
4.0 DIAGNOSTIC FEATURES ................................................................................................................... 31
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 31
F
IGURE
18. S
ERIAL
R
EMOTE
L
OOPBACK
......................................................................................................................................... 31
4.2 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 31
F
IGURE
19. D
IGITAL
L
OCAL
L
OOPBACK
........................................................................................................................................... 31
4.3 ANALOG LOCAL LOOPBACK ...................................................................................................................... 32
F
IGURE
20. A
NALOG
L
OCAL
L
OOPBACK
.......................................................................................................................................... 32
4.4 SPLIT LOOPBACK ......................................................................................................................................... 32
F
IGURE
21. S
PLIT
L
OOPBACK
......................................................................................................................................................... 32
4.5 EYE DIAGRAM ............................................................................................................................................... 33
F
IGURE
22. T
RANSMIT
E
LECTRICAL
O
UTPUT
E
YE
D
IAGRAM
............................................................................................................. 33
4.6 SONET JITTER REQUIREMENTS ................................................................................................................. 33
4.6.1 JITTER TOLERANCE: ................................................................................................................................................ 33
F
IGURE
23. GR-253 J
ITTER
T
OLERANCE
M
ASK
.............................................................................................................................. 34
T
ABLE
18: XRT91L31 R
ECEIVER
J
ITTER
T
OLERANCE
P
ERFORMANCE
............................................................................................. 34
F
IGURE
24. J
ITTER
T
OLERANCE
F
OR
OC-12
WITH
H
IGH
B
ANDWIDTH AND
L
OW
B
ANDWIDTH
S
ETTINGS
............................................ 35
F
IGURE
25. J
ITTER
T
OLERANCE
F
OR
OC-3
WITH
H
IGH
B
ANDWIDTH AND
L
OW
B
ANDWIDTH
S
ETTINGS
.............................................. 35
4.6.2 JITTER TRANSFER .................................................................................................................................................... 35
F
IGURE
26. J
ITTER
T
RANSFER
F
OR
OC-12 .................................................................................................................................... 36
F
IGURE
27. J
ITTER
T
RANSFER
F
OR
OC-3 ...................................................................................................................................... 36
4.6.3 JITTER GENERATION................................................................................................................................................ 36
T
ABLE
19: XRT91L31 O
PTICAL
J
ITTER
G
ENERATION USING
223-1 PRBS
PATTERN
........................................................................ 37
T
ABLE
20: XRT91L31 O
PTICAL
J
ITTER
G
ENERATION USING
223-1 PRBS
PATTERN USING
A
LTERNATE
S
TANDARD
F
ILTERS
............. 37
5.0 ELECTRICAL CHARACTERISTICS ................................................................................................... 37
A
BSOLUTE
M
AXIMUM
RATINGS .................................................................................................................. 37
ABSOLUTE MAXIMUM POWER AND INPUT/OUTPUT RATINGS ......................................................... 37
POWER AND CURRENT DC E
LECTRICAL
C
HARACTERISTICS
.................................................................... 38
................................................................................................................................................................... 38
LVPECL AND LVTTL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS...................................... 39
F
IGURE
28. D
IFFERENTIAL VOLTAGE SWING DEFINITIONS
(I
NPUT OR OUTPUT
)
FOR CLOCK AND DATA
................................................. 40
ORDERING INFORMATION .................................................................................................................. 40
PACKAGE DIMENSIONS ................................................................................................ 40
F
IGURE
29. P
ACKAGE
D
IMENSIONS
................................................................................................................................................ 40
R
EVISION
H
ISTORY
...................................................................................................................................... 41
T
ABLE
21: .................................................................................................................................................................................... 41
5
