1442, 1445, 1446
Vishay Foil Resistors
Bulk Metal
®
Foil Technology
Dual-In-Line Hermetic Resistor Networks
Vishay Model 1442, 1445 and 1446 networks incorporate all
the performance features of Vishay Bulk Metal
®
Foil
technology. The 8, 14 and 16 pin side brazed DIPs are a
ceramic package. Ceramic has the advantage of electrical
isolation on the underside, and, in DIP form, a favorable pin
arrangement when two networks are to be placed side by
side and connected together.
Review data sheet "7 Technical Reasons to Specify Bulk
Metal
®
Foil Resistor Networks."
Networks are built to your requirements. Send your
schematic and electrical requirements to the Applications
Engineering Department. (See data sheet "Network
Worksheet.") A unique part number will be assigned which
defines all aspects of your network.
Product may not be to scale
FIGURE 1 - PACKAGE SIZES AND CHARACTERISTICS
L
B
0.200 MAXIMUM
(5.08)
LL
NO. 1 LEAD
0.015 to 0.022
(0.38 to 0.56)
0.100
TYPICAL
(2.54)
0.008 to 0.016
(0.20 to 0.41)
W
0.300 ± 0.010
(7.62 ± 0.25)
NOTE:
1. These networks utilize Vishay Bulk Metal
®
Foil resistor chips V5X5 and V15X5 or VTF15X5 Thin Film chips.
2. The V5X5 and V15X5 chips have maximum resistance values of 10K and 33K respectively in Bulk Metal
®
Foil and 500K in VTF15X5 Thin
Film chips.
3. The V5X5 and V15X5 chip(s) can be intermixed in a package.
VISHAY
MODEL
1442
1445
1446
NO. OF
PINS
8
14
16
MAXIMUM DIMENSIONS IN INCHES (MM)
L
0.520 ± 0.020
(13.21 ± 0.51)
0.740 ± 0.045
(18.80 ± 1.14)
0.780 ± 0.030
(19.81 ± 0.76)
W
0.295 ± 0.010
(7.49 ± 0.025)
0.270 + 0.035/- 0.030
(6.86 + 0.89/- 0.76)
0.290 ± 0.008
(7.37 ± 0.20)
H
0.054
(1.37)
0.046
(1.17)
0.040 to 0.070
(1.01 to 1.78)
LL
0.125 minimum
(3.18)
0.135 + 0.015/- 0.010
(3.43 + 0.38/- 0.25)
0.135 + 0.015/- 0.010
(3.43 + 0.38/- 0.25)
CHIP
CAPACITY
V5X5
12
30
36
V15X5
4
10
12
MAXIMUM POWER RATING
(WATTS)
AT + 70 °C
0.4
1.2
1.4
FIGURE 2 - SAMPLE CIRCUIT DESIGN AND CHIP LAYOUT
NOTE:
Usable area is represented by the dotted lines
- a rectangle 0.150 Inches x 0.200 Inches.
Illustrations not to scale. Chips shown
undersize for clarity. Drawing view is from the
top looking down into the package.
7
6
8
8
5
7
6
5
1
4
1
2
3
2
3
4
www.foilresistors.com
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For any questions, contact:
foil@vishaypg.com
Document Number: 63032
Revision: 24-Mar-10
1442, 1445, 1446
Vishay Foil Resistors
FIGURE 3 - SAMPLE CIRCUIT DESIGNS AND CHIP LAYOUTS
NOTE:
Usable area is represented by the dotted lines - a rectangle 0.150 Inches x 0.500 Inches. Illustrations not to scale.
Chips shown undersize for clarity. Drawing view is from the top looking down into the package.
TWO DECADES OF BCD LADDER
PLUS TWO SCALING RESISTORS
14
13
12
11
10
9
8
14
FOUR DIVIDERS PLUS
APPLICATION RESISTOR
13
12
11
10
9
8
14
TEN RESISTOR DIVIDER
13
12
11
10
9
8
R10 R1 R2 R3 R4 R5 R6 R7 R8 R9
R1 R2 R3 R4 R5 R6 R7 R8
R9
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
1
2
3
13
4
5
6
6
8
7
14
1
2
1
14
3
13
4
4
11
5
10
6
8
7
1
2
3
4
5
6
7
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
R1 R2 R3 R4
R5 R6 R7 R8
R9 R10
R1
R3 R5
R7
R9
2
3
4
5
12 11 10 9
7
1
R2
2
3
R4 R6
12
5
6
9
R8
7
1
14
2
12
4
11
5
10
6
8
7
FIGURE 4 - SAMPLE CIRCUIT DESIGNS AND CHIP LAYOUTS
NOTE:
Usable area is represented by the dotted lines - a rectangle 0.150 Inches x 0.600 Inches. Illustrations not to scale. Chips shown undersize for
clarity. Drawing view is from the top looking down into the package.
16 15 14 13 12 11 10
9
R1 R2 R3 R4 R5 R6 R7 R8 R9 R
10
R
11
ELEVEN RESISTOR
DIVIDER
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11
1 16 2 15 4 13 5 12 7 10 8 9
1
2
3
4
5
6
7
8
16 15 14 13 12 11 10
9
EIGHT RESISTOR
PACKAGE
R1 R2
R3
R4 R5
R6 R7
R8
16 15 14 13 12 11 10
R1
R2
R3
R4
R5
R6
R7
9
R8
1
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
Document Number: 63032
Revision: 24-Mar-10
For any questions, contact:
foil@vishaypg.com
www.foilresistors.com
2
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Vishay Precision Group
Disclaimer
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Document No.: 63999
Revision: 27-Apr-11
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1