V59C1G01(408/808/168)QB
HIGH PERFORMANCE 1Gbit DDR2 SDRAM
8 BANKS X 32Mbit X 4 (408)
8 BANKS X 16Mbit X 8 (808)
8 BANKS X 8Mbit X 16 (168)
3
DDR2-667
Clock Cycle Time (t
CK3
)
Clock Cycle Time (t
CK4
)
Clock Cycle Time (t
CK5
)
Clock Cycle Time (t
CK6
)
Clock Cycle Time (t
CK7
)
System Frequency (f
CK max
)
5ns
3.75ns
3ns
3ns
3ns
333 MHz
25A
DDR2-800
5ns
3.75ns
3ns
2.5ns
2.5ns
400 MHz
25
DDR2-800
5ns
3.75ns
2.5ns
2.5ns
2.5ns
400 MHz
PRELIMINARY
19A
DDR2-1066
5ns
3.75ns
3ns
2.5ns
1.875ns
533 MHz
Features
■
High speed data transfer rates with system frequency
up to 533 MHz
■
8 internal banks for concurrent operation
■
4-bit prefetch architecture
■
Programmable CAS Latency: 3, 4 ,5 , 6 and 7
■
Programmable Additive Latency:0, 1, 2, 3 , 4, 5 and 6
■
Write Latency=Read Latency-1
■
Programmable Wrap Sequence: Sequential
or Interleave
■
Programmable Burst Length: 4 and 8
■
Automatic and Controlled Precharge Command
■
Power Down Mode
■
Auto Refresh and Self Refresh
■
Refresh Interval: 7.8 us (8192 cycles/64 ms) Tcase
between 0
o
C and 85
o
C
■
OCD (Off-Chip Driver Impendance Adjustment)
■
ODT (On-Die Termination)
■
Weak Strength Data-Output Driver Option
■
Bidirectional differential Data Strobe (Single-ended
data-strobe is an optional feature)
■
On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■
DQS can be disabled for single-ended data strobe
■
Read Data Strobe (RDQS) supported (x8 only)
■
Differential clock inputs CK and CK
■
JEDEC Power Supply 1.8V ± 0.1V
■
VDDQ=1.8V ± 0.1V
■
Available in 68-ball FBGA for x4 and x8 component or
84-ball FBGA for x16 component
■
RoHS compliant
■
PASR Partial Array Self Refresh
■
tRAS lockout supported
Description
The V59C1G01(408/808/168)QB is a eight bank DDR
DRAM organized as 8 banks x 32Mbit x 4 (408), 8 banks x
16Mbit x 8 (808), or 8 banks x 8Mbit x 16 (168). The
V59C1G01(408/808/168)QB achieves high speed data
transfer rates by employing a chip architecture that
prefetches multiple bits and then synchronizes the output
data to a system clock.
The chip is designed to comply with the following key
DDR2 SDRAM features:(1) posted CAS with additive la-
tency, (2)write latency=read latency-1, (3)Off-chip Driv-
er(OCD) impedance adjustment, (4) On Die Termination.
All of the control, address, circuits are synchronized
with the positive edge of an externally supplied clock. I/O
s are synchronized with a pair of bidirectional strobes
(DQS, DQS) in a source synchronous fashion.
Operating the eight memory banks in an interleaved
fashion allows random access operation to occur at a
higher rate than is possible with standard DRAMs. A se-
quential and gapless data rate is possible depending on
burst length, CAS latency and speed grade of the device.
Available Speed
Table 1:
Grade
Grade
-3 (DDR2-667)
-25A (DDR2-800)
-25 (DDR2-800)
-19A (DDR2-1066)
CL
5
6
5
7
tRCD
5
6
5
7
tRP
5
6
5
7
Unit
CLK
CLK
CLK
CLK
Device Usage Chart
Operating
Temperature
Range
0°C to 85°C
V59C1G01(408/808/168)QB Rev.1.0 June 2008
Package Outline
68 ball FBGA
84 ball FBGA
•
CK Cycle Time (ns)
-3
•
Power
Std.
•
-25A
•
-25
•
-19A
•
L
•
Temperature
Mark
Blank
1
ProMOS TECHNOLOGIES
DDR Part Number
1
2
3
4
5
6
7
8
9 10
11
12
13
V59C1G01(408/808/168)QB
14
15
16 17 18
19
V
ProMOS
5 9
C
1
G 0 1 8 0
ORGANIZATION
& REFRESH
64Mx4, 8K : 25640
32Mx8, 8K : 25680
128Mx4, 8K : 51240
64Mx8, 8K : 51280
32Mx16, 8K : 51216
16Mx16, 8K : 25616
8
Q
B
J
2 5
TEMPERATURE
BLANK:
0 - 85 C
-40 - 85 C
-40 - 105 C
-40 - 125 C
I:
64Mx16, 8K : G0116
TYPE
59 : DDR2
CMOS
256Mx4, 8K : G0140
128Mx8, 8K : G0180
H:
E:
SPEED
5 : 200MHz @CL3-3-3
VOLTAGE
1:
1.8 V
BANKS
4 : 4 BANKS
8 : 8 BANKS
I/O
Q: SSTL_18
REV CODE
37 : 266MHz @CL4-4-4
3 : 333MHz @CL5-5-5
25 : 400MHz @CL5-5-5
25A : 400MHz @CL6-6-6
19 : 533MHz @CL6-6-6
19A : 533MHz @CL7-7-7
SPECIAL FEATURE
L : LOW POWER GRADE
U : ULTRA LOW POWER GRADE
F
J
P
PACKAGE
RoHS Green
PACKAGE
DESCRIPTION
FBGA
Die-stacked FBGA
*RoHS: Restriction of Hazardous Substances
*GREEN: RoHS-compliant and Halogen-Free
1Gb
Confi gura tion
# of Bank
Bank Address
Auto precharge
Row Address
Column Address
256Mb x 4
8
BA0 ~ BA2
A
10
/AP
A
0
~ A
13
A
0
~ A
9,
A
11
128Mb x 8
8
BA0 ~ BA2
A
10
/AP
A
0
~ A
13
A
0
~ A
9
64Mb x1 6
8
BA0 ~ BA2
A
10
/AP
A
0
~ A
12
A
0
~ A
9
V59C1G01(408/808/168)QB Rev. 1.0 June 2008
2
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QB
256Mx4 DDR2 Pin Configuration
(Top view: see balls through package)
1
NC
2
NC
3
A
B
C
D
7
8
NC
9
NC
VDD
NC
VDDQ
NC
VDDL
NC
VSSQ
DQ1
VSSQ
VREF
CKE
VSS
DM
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VDDQ
NC
VDDQ
NC
VDD
ODT
BA2
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
NC
NC
W
NC
NC
V59C1G01(408/808/168)QB Rev. 1.0 June 2008
3
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QB
128Mx8 DDR2 PIN CONFIGURATION
(Top view: see balls through package)
1
NC
2
NC
3
A
B
C
D
7
8
NC
9
NC
VDD
DQ6
VDDQ
DQ4
VDDL
NU/RDQS
VSSQ
DQ1
VSSQ
VREF
CKE
VSS
DM/RDQS
VDDQ
DQ3
VSS
WE
BA1
A1
A5
A9
NC
E
F
G
H
J
K
L
M
N
P
R
T
U
V
VSSQ
DQS
VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
DQS
VSSQ
DQ0
VSSQ
CK
CK
CS
A0
A4
A8
A13
VDDQ
DQ7
VDDQ
DQ5
VDD
ODT
BA2
BA0
A10
VDD
VSS
A3
A7
VSS
VDD
A12
NC
NC
W
NC
NC
V59C1G01(408/808/168)QB Rev. 1.0 June 2008
4
ProMOS TECHNOLOGIES
V59C1G01(408/808/168)QB
64Mx16 DDR2 PIN CONFIGURATION
(Top view: see balls through package)
1
2
3
7
8
9
VD D
DQ1 4
VD DQ
DQ1 2
VD D
DQ6
VD DQ
DQ4
VD DL
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VRE F
CKE
VS S
UDM
VD DQ
DQ1 1
VS S
LD M
VD DQ
DQ3
VS S
WE
BA1
A1
A5
A9
NC, A14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS Q
UDQS
VDD Q
DQ10
VSS Q
LD QS
VDD Q
DQ2
VSS DL
RA S
CAS
A2
A6
A11
NC, A15
UD QS
VS SQ
DQ8
VS SQ
LD QS
VS SQ
DQ0
VS SQ
CK
CK
CS
A0
A4
A8
NC, A13
VD DQ
DQ1 5
VD DQ
DQ1 3
VD DQ
DQ7
VD DQ
DQ5
VD D
ODT
NC, BA2
BA 0
A1 0/AP
VD D
VS S
A3
A7
VS S
VDD
A1 2
V59C1G01(408/808/168)QB Rev. 1.0 June 2008
5
