Z86D73
40/44/48-Pin Low-Voltage
IR OTP
Preliminary Product Specification
PS019401-1102
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 •
www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition
exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or
service names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
©2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty
and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no
warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No licenses are
conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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40/44/48-Pin Low-Voltage IR OTP
iii
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS (Output, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AS (Output, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R/W Read/Write (Output, Write Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R/RL (Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 0 (P07–P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 1 (P17–P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 2 (P27–P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Port 3 (P37–P31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
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26
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31
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42
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 68
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 72
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PS019401-1102
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List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
40-Pin DIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
44-Pin QFP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
44-Pin PLCC Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
48-Pin SSOP Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External I/O or Memory Read/Write Timing . . . . . . . . . . . . . . . . . . . 13
Additional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 25
Program Memory Map (32K OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 29
Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Register Pointer—Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 47
Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Ping-Pong Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 58
Stop-Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
PS019401-1102
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40/44/48-Pin Low-Voltage IR OTP
v
Figure 35. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 36. Stop-Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 37. Stop-Mode Recovery Register 2 ((0F) DH:D2–D4,
D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 38. Watch-Dog Timer Mode Register (Write Only) . . . . . . . . . . . . . . . .
Figure 39. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 40. TC8 Control Register ((0D) OH: Read/Write
Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 41. T8 and T16 Common Control Functions ((0D) 1h: Read/Write) . . .
Figure 42. T16 Control Register ((0D) 2h: Read/Write
Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 43. Low-Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 44. Stop-Mode Recovery Register ((0F) 0Bh: D6–D0=Write Only,
D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 45. Stop-Mode Recovery Register 2 ((0F) 0Dh:D2–D4,
D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 46. Watch-Dog Timer Register ((0F) 0Fh: Write Only) . . . . . . . . . . . . .
Figure 47. Port Configuration Register (PCON) ((0F) 0h: Write Only) . . . . . . .
Figure 48. Port 2 Mode Register (F6h: Write Only) . . . . . . . . . . . . . . . . . . . . .
Figure 49. Port 3 Mode Register (F7h: Write Only) . . . . . . . . . . . . . . . . . . . . .
Figure 50. Port 0 and 1 Mode Register (F8h: Write Only) . . . . . . . . . . . . . . . .
Figure 51. Interrupt Priority Register (F9h: Write Only) . . . . . . . . . . . . . . . . . .
Figure 52. Interrupt Request Register (FAh: Read/Write) . . . . . . . . . . . . . . . . .
Figure 53. Interrupt Mask Register (FBh: Read/Write) . . . . . . . . . . . . . . . . . . .
Figure 54. Flag Register (FCh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 55. Register Pointer (FDh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 56. Stack Pointer High (FEh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . .
Figure 57. Stack Pointer Low (FFh: Read/Write) . . . . . . . . . . . . . . . . . . . . . . .
Figure 58. 40-Pin DIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 59. 44-Pin PLCC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 60. 44-Pin QFP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 61. 48-Pin SSOP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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PS019401-1102
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stm32/stm8
