Product Update
UP004207-0308
Errata to Z8F640x, Z8F480x,
Z8F320x, Z8F240x, Z8F160x
(Z8 Encore!
®
)
Z8F640x Family Devices with Date Codes 0239 and Later, without
QUAL Topmark
The errata listed in
Table 1
are found in Zilog’s Z8F640x family products (includes Z8F480x, Z8F320x,
Z8F240x, and Z8F160x) without a QUAL topmark and with date codes 0239 and later, where the date
code is YYWW (year and week of assembly). When reviewing the following errata, refer to the most
recent version of the product specification. Data contained in this document is Preliminary only.
Table 1. Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x Errata for Devices with Date
Codes 0239 and Later
Sl
No
1
Summary
The On-Chip
Debugger’s (OCD)
Step, Stuff, and
Execute instructions
do not work if an
interrupt is pending.
Description
The OCD’s Step, Stuff, and Execute instructions do not work if an interrupt is
pending. When in DEBUG mode, the eZ8
TM
CPU will not acknowledge inter-
rupts or DMA requests. However, if an interrupt or DMA request is pending,
the eZ8 CPU will not acknowledge an instruction. If an interrupt is pending and
an OCD Step, Stuff, or Execute instruction is executed, the OCD will wait for-
ever for the eZ8 CPU to acknowledge the opcode because of the pending
interrupt.
Workaround
The OCD must look at the next instruction before single stepping and take
appropriate measures. Instead of executing the Enable Interrupt (EI) instruc-
tion, rewrite the PC to the instruction following the EI and then enable inter-
rupts through a register write to the interrupt control register.
2
Extraneous register There are several instructions during which the CPU performs extra register
reads by the eZ8
reads. Most are addresses the CPU was trying to read, the CPU reads the
CPU.
same register twice. There are a couple instructions where the CPU reads
from random addresses. This is not a problem, unless the register being read
is affected by a read operation. The registers affected by read operations
include the WDTCTL and DMAA_STAT registers and the UART, SPI, and I
2
C
Receive Data registers. If a read occurs on these registers, receive characters
may be lost or the WDT status lost.
Workaround
Do not set RP to %XF.
Also, only use the LDX instruction on peripheral registers affected by read
operations.
3
SPI does not sup-
port single bit data
transfers.
The SPI does not function properly when configured for single-bit data
transfers. This is not a typical SPI data format.
Workaround
None.
Copyright ©2008 by Zilog
®
, Inc. All rights reserved.
www.zilog.com
Errata to Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x (Z8 Encore!
®
)
Table 1. Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x Errata for Devices with Date
Codes 0239 and Later (Continued)
Sl
No
4
Summary
UART Overrun
errors may be
missed.
Description
Framing Error, Parity Error, Break Detect, and Rx Overrun Error conditions are
cleared up on reading the UART Receive Data register. During the time
between reading the UART Status register and the UART Receive Data
register, it is possible for another character to be received. This causes all
UART error flags and the UART Receive Data register to be updated with the
new character. Thus making it possible to miss the Overrun Error.
The window for this error to occur if a UART Overrun Error occurs between the
time the UART Status register is read and the UART Receive Data register is
read. If vectored interrupts are used, the UART should be serviced and
Receiver Overrun conditions should not occur.
If you have long interrupt service routines (ISR) (bad coding style) or are poll-
ing the UART instead of using vectored interrupts, Overrun errors become
more likely. The window for this problem to occur is still small, yet becomes
more probable if UART Receiver Overrun conditions occur frequently.
Workaround
When the user code employs vectored interrupts for the UART and does not
have long ISR, this is not a problem. Even for long ISR, the problem can be
avoided by,
• Nesting the ISR
• Adjusting the interrupt masks and re-enabling interrupts
5
Interrupts can be
lost if received by
the interrupt control-
ler at the same time
as a write to the
corresponding IRQ
register.
Incoming interrupts can be lost if received by the interrupt controller at the
same time as a write to the corresponding IRQ register.
Workaround
Clear the Continuous Assertion interrupts using a two-step interrupt service
process. In the ISR, first check if the interrupt source (for example, the UART)
really has a pending interrupt. If yes:
• Process the interrupt as usual.
• Clear the interrupt at the source (for example, at the UART).
• Do not clear the IRQ register bit (this would make it possible to miss
another incoming interrupt).
• Execute a return from the ISR.
After this first pass through the ISR, the IRQ register bit will still be set to 1.
This will cause the interrupt to occur again. When the Z8 Encore! vectors to
the interrupt, check if the interrupt source (for example, the UART) really has a
pending interrupt. If there is no pending interrupt, immediately execute a
return from the ISR.
UP004207-0308
Page 2 of 15
Errata to Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x (Z8 Encore!
®
)
Table 1. Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x Errata for Devices with Date
Codes 0239 and Later (Continued)
Sl
No
6
Summary
The TXST bit in the
SPISTAT register
does not assert until
the transmission
actually starts.
Description
When data is written to the SPIDATA register to be transmitted, the TXST bit in
the SPISTAT register does not assert until the transmission actually starts
which results in a short delay (delay is dependent on the baud rate). It is
possible for software to poll the TXST bit and see a 0 before the transmission
has started. Software may erroneously conclude that the data has already
been transmitted.
Workaround
User code can poll the IRQ bit in the SPISTAT register. Even when the SPI
interrupt is disabled, the IRQ bit will assert at the end of the data transaction
and remain asserted until cleared by software.
7
Reading the UART
Status 1 register
through the OCD
always returns the
value
00H.
The UART Status 1 register is cleared when read. When the OCD reads the
register it holds the read for multiple system clock cycles, thereby clearing the
value before completing the read. Thus, the value returned through the OCD
is always
00H.
This issue affects only OCD operation and does not affect nor-
mal operation.
Workaround
Issue a CPU command through the OCD to transfer the UART Status 1
register data to a Register File location. Then the desired UART Status 1
register data can be read from the Register File.
8
When used as
simple timers, the
Baud Rate
Generators in the
UARTs, I
2
C, and SPI
generate a
spurious interrupt at
the beginning of the
count.
When the Baud Rate Counters for UARTs, I
2
C, and SPI are placed in timer
mode they immediately generate an interrupt. This is because the counters
are incorrectly reset to
0001H
rather than the reload value. Since
0001H
is the
reload state, it initiates an interrupt request.
Workaround
•
•
•
•
Use one of the four other Timers rather than the Baud Rate Generators in
timer mode.
Delay enabling the interrupt for these counters until the count value has
progressed beyond
0001H.
Write the ISR so that is disregards the first interrupt.
Clear the associated interrupt request in the Interrupt Control shortly after
starting the timer.
UP004207-0308
Page 3 of 15
Errata to Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x (Z8 Encore!
®
)
Table 1. Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x Errata for Devices with Date
Codes 0239 and Later (Continued)
Sl
No
9
Summary
SPI operating as a
Slave in a multi-
Slave system can
lose transmit data.
Description
If the SPI devices on the Z8 Encore!
®
is configured as a Slave device in a
multi-Slave system, the SPI data can be corrupted by transfers to and from the
Master to other Slaves sharing the same SPI pins. Even though the SS input
pin is High (that is, not selecting the Z8 Encore!'s SPI device), the data will be
shifted into the SPI’s receive buffer. This can overwrite any data that has been
placed in the SPI's transmit buffer by the eZ8 CPU in preparation for transmit
out from the SPI Slave.
Workaround
If it is desired to use the SPI device as a Slave in multi-Slave systems, the
SCK input signal to the Z8 Encore! should be disabled externally when the SS
signal is High. This will prevent shifting in of data by the SPI Slave receiver
when not selected.
10
ADC output is
inaccurate for input
values below
approximately
20 mV.
The output from the ADC can vary widely when the input signal drops below
about 20 mV.
Workaround
Measure analog inputs only above 20 mV.
11
The following instructions have timing errors in which an extra (unused) clock
eZ8 CPU opcode
timing is incorrect for cycle is inserted during instruction execution:
three Load
instructions.
Instruction Opcode Spec Cycles Actual Cycles
LD
E4
2
3
LD
E7
3
4
LD
E5
3
4
Workaround
None. This issue is not likely to affect the user code. If the user code has soft-
ware timing loops, it is possible that future Z8 Encore! products will have dif-
ferent loop timing using the same code. Due the pipelined nature of the eZ8
CPU, timing loops are less likely to be employed than on older Z8
®
products.
12
GPIO Port pins draw
current when input
voltage exceeds one
diode drop above
the supply voltage.
For the 5 V-input tolerant GPIO pins, when the input voltage exceeds
approximately 4.0 V (for a 3.3 V supply voltage), current will be drawn by the
input pin.
Workaround
For GPIO pins that toggle at low frequencies, a 10 kΩ resistor can be placed
between the GPIO pin and the external driver. This will limit the current into the
pin to about 150 µA. For higher frequencies, a 1 kΩ resistor should be used.
This will limit the input current to the pin to about 1.5 mA.
UP004207-0308
Page 4 of 15
Errata to Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x (Z8 Encore!
®
)
Table 1. Z8F640x, Z8F480x, Z8F320x, Z8F240x, Z8F160x Errata for Devices with Date
Codes 0239 and Later (Continued)
Sl
No
13
Summary
With the SPI
configured for multi-
master operation, an
occurrence of multi-
master collision will
not be detected.
Description
With the SPI configured for multi-master operation, a multi-master collision,
should it occur, will not be detected by the Z8 Encore!’s SPI device.
Workaround
A GPIO pin, configured as an input with interrupt on a falling edge, could
potentially be used to detect multi-master collisions. If the interrupt occurs with
the SPI configured as a Master, the user software could determine that a multi-
master collision has likely occurred.
The UART Receiver and Transmitter incorrectly test for the setting of the
Parity Enable (PEN) bit when in MP mode. The UART is not supposed to use
parity when the MP bit is enabled.
Workaround
When operating in MP mode, the user code should disable parity by clearing
the PEN bit in the UART Control 0 register.
Data written to the I
2
C Data register for transmission cannot be read back.
This is unlikely to affect user operation at all.
Workaround
None. Generally, the user code does not need to read back the data that was
written to the I
2
C Data register for transmission.
If an interrupt is pending and a software TRAP or an illegal instruction TRAP is
executed, the highest priority pending interrupt will be erroneously cleared.
This causes interrupts to be lost.
Workaround
Do not execute a software TRAP instruction.
When configured as inputs, the GPIO pins source high (50+ µA) current when
the input voltage on the pin is near mid-range. If a high impedance device is
used to drive the input, this can result in logic errors due to the resistive divider
effect of the current source and the external impedance.
Workaround
Do not drive the GPIO port input pins with high-impedance drivers (greater
than approximately 20 kΩ).
14
The UART Receiver
and Transmitter
incorrectly test for
the setting of the
Parity Enable bit
when in Multiproces-
sor (MP) mode.
Data written to the
I
2
C Data register
cannot be read
back.
15
16
Execution of a soft-
ware TRAP instruc-
tion may
erroneously clear
pending interrupts.
Driving the GPIO
port pins with a high-
impedance source
may result in logic
errors.
17
UP004207-0308
Page 5 of 15
