ZL30116
SONET/SDH
OC-48/OC-192 System Synchronizer
Data Sheet
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June 2006
Ordering Information
ZL30116GGG
ZL30116GGG2
100 Pin CABGA
100 Pin CABGA*
Trays
Trays
Features
•
Supports the requirements of Telcordia GR-253 and
GR-1244 for Stratum 3, 4E, 4 and SMC clocks, and
the requirements of ITU-T G.781 SETS, G.813
SEC, G.823, G.824 and G.825 clocks
Internal APLL provides standard output clock
frequencies up to 622.08 MHz that meet jitter
requirements for interfaces up to OC-192/STM-64
Programmable output synthesizers generate clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
Provides two DPLLs which are independently
configurable through a serial software interface
DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover),
selectable loop bandwidth and pull-in range
DPLL2 provides a comprehensive set of features
necessary for generating derived output clocks and
other general purpose clocks
*Pb Free Tin/Silver/Copper
-40
o
C to +85
o
C
•
Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
Supports master/slave configuration for
AdvancedTCA
TM
Configurable input to output delay and output to
output phase alignment
Optional external feedback path provides dynamic
input to output delay compensation
Provides 3 sync inputs for output frame pulse
alignment
Generates several styles of output frame pulses
with selectable pulse width, polarity and frequency
Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
Supports IEEE 1149.1 JTAG Boundary Scan
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trst_b tck tdi tms
tdo
dpll2_ref
dpll1_hs_en
dpll1_lock dpll1_holdover
diff0_en
diff1_en
osco
osci
Master
Clock
IEEE 1449.1
JTAG
ref
DPLL2
P0
Synthesizer
P1
Synthesizer
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
diff0_p/n
diff1_p/n
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
ref7:0
ref
DPLL1
sync2:0
Reference
Monitors
ref_&_sync_status
sync
fb_clk
fb_fp
SONET/SDH
APLL
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
fb_clk
Feedback
Synthesizer
int_b
SPI Interface
Controller &
State Machine
ext_fb_fp
ext_fb_clk
sck
si
so
cs_b
rst_b
slave_en
dpll1_mod_sel1:0
sdh_filter
filter_ref0
filter_ref1
Figure 1 - Block Diagram
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL30116
Applications
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AdvancedTCA
TM
Systems
Multi-Service Edge Switches or Routers
Multi-Service Provisioning Platforms (MSPPs)
Add-Drop Multiplexers (ADMs)
Wireless/Wireline Gateways
Wireless Base Stations
DSLAM / Next Gen DLC
Core Routers
Data Sheet
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Zarlink Semiconductor Inc.
ZL30116
Table of Contents
Data Sheet
1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.2 DPLL Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.7 Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.8 External Feedback Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Zarlink Semiconductor Inc.
ZL30116
List of Figures
Data Sheet
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6 - Output Clock Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - Phase Delay Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8 - Typical Master/Slave Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9 - External Feedback Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Zarlink Semiconductor Inc.
ZL30116
List of Tables
Data Sheet
Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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