CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
5. Voltage measured with respect to SGND.
6.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
7. For
θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
8. Includes margin limits.
Electrical Specifications
V
DD
= 12V, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at T
A
= +25°C.
Boldface limits
apply over the operating temperature range, -40°C to +85°C.
CONDITIONS
MIN
(Note 19)
TYP
MAX
(Note 19)
UNIT
PARAMETER
INPUT AND SUPPLY CHARACTERISTICS
I
DD
Supply Current at f
SW
= 200kHz
I
DD
Supply Current at f
SW
= 1.4MHz
I
DDS
Shutdown Current
VR Reference Output Voltage
V25 Reference Output Voltage
OUTPUT CHARACTERISTICS
Output Voltage Adjustment range (Note 9)
Output Voltage Set-point Resolution (Note 10)
V
IN
> V
OUT
Set using resistors
GH, GL no load;
MISC_CONFIG[7] = 1
EN = 0V
No I
2
C/SMBus activity
V
DD
> 6V, I
VR
< 20mA
V
R
> 3V, I
V25
< 20mA
–
–
–
4.5
2.25
16
25
6.5
5.2
2.5
30
50
9
5.5
2.75
mA
mA
mA
V
V
0.6
–
–
-1
–
-100
- 50
-100
-1
-100
–
10
±0.025
–
110
–
–
–
–
–
5.0
–
–
1
200
100
50
100
1
100
V
mV
% FS
(Note 10)
%
µA
mV
mV
µA
µA
µA
Set using I
2
C/SMBus
Output Voltage Accuracy (Note 11)
VSEN input Bias Current
Current Sense Differential Input
Voltage (Ground Referenced)
Includes line, load, temp
VSEN = 5.5V
V
ISENA
- V
ISENB
Current Sense Differential Input Voltage
V
ISENA
- V
ISENB
(V
OUT
Referenced; V
OUT
must be less than 4.0V)
Current Sense Input Bias Current
Current Sense Input Bias Current
(V
OUT
Referenced, V
OUT
< 4.0 V)
Ground referenced
ISENA
ISENB
3
FN6876.3
August 29, 2012
ZL6100
Electrical Specifications
V
DD
= 12V, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at T
A
= +25°C.
Boldface limits
apply over the operating temperature range, -40°C to +85°C.
(Continued)
CONDITIONS
Set using DLY pin or resistor
Set using I
2
C/SMBus
Soft-start Delay Duration Accuracy
Turn-on delay (precise mode) (Notes 12, 13)
Turn-on delay (normal mode) (Note 14)
Turn-off delay (Note 14)
Soft-start Ramp Duration Range
Set using SS pin or resistor
Set using I
2
C pin
Soft-start Ramp Duration Accuracy
LOGIC INPUT/OUTPUT CHARACTERISTICS
Logic Input Leakage Current
Logic Input Low, V
IL
Logic Input OPEN (N/C)
Logic Input high, V
IH
Logic Output Low, V
OL
Logic Output High, V
OH
I
OL
≤
4mA (Note 18)
I
OH
≥
-2mA (Note 18)
Multi-mode logic pins
Push-Pull Logic pins
-250
–
–
2.0
–
2.25
–
–
1.4
–
–
–
250
0.8
–
–
0.4
–
nA
V
V
V
V
V
MIN
(Note 19)
2
0.002
–
–
–
0
0
–
TYP
–
–
±0.25
-1/+5
-1/+5
–
–
100
MAX
(Note 19)
200
500
–
–
–
200
200
–
UNIT
ms
s
ms
ms
ms
ms
ms
µs
PARAMETER
Soft-start Delay Duration Range (Note 12)
OSCILLATOR AND SWITCHING CHARACTERISTICS
Switching Frequency Range
Switching Frequency Set-point Accuracy
Maximum PWM Duty Cycle
Minimum SYNC Pulse Width
Input Clock Frequency Drift Tolerance
GATE DRIVERS
High-side Driver Voltage
High-side Driver Peak Gate Drive Current
(Pull-down)
High-side Driver Pull-up Resistance
High-side Driver Pull-down Resistance
Low-side Driver Peak Gate Drive Current
(Pull-up)
Low-side Driver Peak Gate Drive
Current (pull-down)
Low-side Driver Pull-up Resistance
Low-side Driver Pull-down Resistance
SWITCHING TIME
GH Rise and Fall time
GL Rise and Fall time
TRACKING
VTRK Input Bias Current
VTRK Tracking Ramp Accuracy
VTRK Regulation Accuracy
FAULT PROTECTION CHARACTERISTICS
UVLO Threshold Range
Configurable via I
2
C/SMBus
2.85
–
16
V
VTRK = 5.5V
100% Tracking, V
OUT
- VTRK
100% Tracking, V
OUT
- VTRK
–
-100
-1
110
–
–
200
+100
1
µA
mV
%
(V
BST
- V
SW
) = 4.5V, C
LOAD
= 2.2nF
V
R
= 5V, C
LOAD
= 2.2nF
–
–
5
5
20
20
ns
ns
(V
BST
- V
SW
)
(V
BST
- V
SW
) = 4.5V
(V
BST
- V
SW
) = 4.5V, (V
BST
- V
GH
) = 50mV
(V
BST
- V
SW
) = 4.5V, (V
GH
- V
SW
) = 50mV
V
R
= 5V
V
R
= 5V
V
R
= 5V, (V
R
- V
GL
) = 50mV
V
R
= 5V, (V
GL
- PGND) = 50mV
–
2
–
–
–
–
–
–
4.5
3
0.8
0.5
2.5
1.8
1.2
0.5
–
–
2
2
–
–
2
2
V
A
Ω
Ω
A
A
Ω
Ω
External clock source
Predefined settings (see Table 12)
Factory default
200
-5
95
150
-13
–
–
–
–
–
1400
5
–
–
13
kHz
%
%
ns
%
4
FN6876.3
August 29, 2012
ZL6100
Electrical Specifications
V
DD
= 12V, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at T
A
= +25°C.
Boldface limits
apply over the operating temperature range, -40°C to +85°C.
(Continued)
CONDITIONS
MIN
(Note 19)
-150
Factory default
Configurable via I
2
C/SMBus
UVLO Delay
Power-Good V
OUT
Threshold
Power-Good V
OUT
Hysteresis
Power-Good Delay
Factory default
Factory default
Using pin-strap or resistor (Note 15)
Configurable via I
2
C/SMBus
VSEN Undervoltage Threshold
Factory default
Configurable via I
2
C/SMBus
VSEN Overvoltage Threshold
Factory default
Configurable via I
2
C/SMBus
VSEN Undervoltage Hysteresis
VSEN Undervoltage/Overvoltage Fault
Response Time
Current Limit Set-point Accuracy
(V
OUT
Referenced)
Current Limit Set-point Accuracy
(Ground referenced)
Current Limit Protection Delay
Factory default
Configurable via I
2
C/SMBus
Temperature Compensation of
Current Limit Protection Threshold
Thermal Protection Threshold
(Junction Temperature)
Thermal Protection Hysteresis
NOTES:
9. Does not include margin limits.
10. Percentage of Full Scale (FS) with temperature compensation applied.
11. V
OUT
measured at the termination of the VSEN+ and VSEN- sense points.
12. The device requires a delay period following an enable signal and prior to ramping its output. Precise timing mode limits this delay period to
approx 2ms, where in normal mode it may vary up to 4ms.
13. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
14. The devices may require up to a 4ms delay following the assertion of the enable signal (normal mode) or following the de-assertion of the enable
signal.
15. Factory default Power-Good delay is set to the same value as the soft-start ramp time.
16. Percentage of Full Scale (FS) with temperature compensation applied.
17. t
SW
= 1/f
SW
, where f
SW
is the switching frequency.
18. Normal capacitance of logic pins is 5pF.
19. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
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