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ispLSI 5256VE

In-System Programmable

3.3V SuperWIDE™ High Density PLD

Features

• Second Generation SuperWIDE HIGH DENSITY

IN-SYSTEM PROGRAMMABLE LOGIC DEVICE

— 3.3V Power Supply

— User Selectable 3.3V/2.5V I/O

— 12000 PLD Gates / 256 Macrocells

— Up to 144 I/O Pins

— 256 Registers

— High-Speed Global Interconnect

— SuperWIDE Generic Logic Block (32 Macrocells) for

Optimum Performance

— SuperWIDE Input Gating (68 Inputs) for Fast

Counters, State Machines, Address Decoders, etc.

— PCB Efficient Ball Grid Array (BGA) Package Options

— Interfaces with Standard 5V TTL Devices

• HIGH PERFORMANCE E

CMOS

TECHNOLOGY

—

max

= 165 MHz Maximum Operating Frequency

—

= 6.0 ns Propagation Delay

— TTL/3.3V/2.5V Compatible Input Thresholds and

Output Levels

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Programmable Speed/Power Logic Path Optimization

• IN-SYSTEM PROGRAMMABLE

— Increased Manufacturing Yields, Reduced Time-to-

Market, and Improved Product Quality

— Reprogram Soldered Devices for Faster Debugging

• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND

3.3V IN-SYSTEM PROGRAMMABLE

• ARCHITECTURE FEATURES

— Enhanced Pin-Locking Architecture with Single-

Level Global Routing Pool and SuperWIDE GLBs

— Wrap Around Product Term Sharing Array Supports

up to 35 Product Terms Per Macrocell

— Macrocells Support Concurrent Combinatorial and

Registered Functions

— Macrocell Registers Feature Multiple Control

Options Including Set, Reset and Clock Enable

— Four Dedicated Clock Input Pins Plus Macrocell

Product Term Clocks

— Programmable I/O Supports Programmable Bus

Hold, Pull-up, Open Drain and Slew Rate Options

— Four Global Product Term Output Enables, Two

Global OE Pins and One Product Term OE per

Macrocell

Functional Block Diagram

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Boundary

Scan

Interface

Generic

Logic Block

Generic

Logic Block

Input Bus

Global Routing Pool

(GRP)

Generic

Logic Block

Generic

Logic Block

Input Bus

Generic

Logic Block

Generic

Logic Block

Input Bus

ispLSI 5000VE Description

The ispLSI 5000VE Family of In-System Programmable

High Density Logic Devices is based on Generic Logic

Blocks (GLBs) of 32 registered macrocells and a single

Global Routing Pool (GRP) structure interconnecting the

GLBs.

Outputs from the GLBs drive the Global Routing Pool

(GRP) between the GLBs. Switching resources are pro-

vided to allow signals in the Global Routing Pool to drive

any or all the GLBs in the device. This mechanism allows

fast, efficient connections across the entire device.

Each GLB contains 32 macrocells and a fully populated,

programmable AND-array with 160 logic product terms

and three extra control product terms. The GLB has 68

inputs from the Global Routing Pool which are available

in both true and complement form for every product term.

The 160 product terms are grouped in 32 sets of five and

sent into a Product Term Sharing Array (PTSA) which

allows sharing up to a maximum of 35 product terms for

a single function. Alternatively, the PTSA can be by-

passed for functions of five product terms or less. The

three extra product terms are used for shared controls:

reset, clock, clock enable and output enable.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

January 2002

5256ve_10

Specifications

ispLSI 5256VE

Functional Block Diagram

Figure 1. ispLSI 5256VE Functional Block Diagram (144-I/O Option)

I/O 143

I/O 142

I/O 141

I/O 140

I/O 129

I/O 128

I/O 127

I/O 126

I/O 125

I/O 124

I/O 123

I/O 122

I/O 111

I/O 110

I/O 109

I/O 108

GOE0

GOE1

Input Bus

Generic

Logic Block

Input Bus

Generic

Logic Block

Boundary

Scan

Interface

TMS

TCK

TDI

TDO

VCCIO

1TOE

I/O 1

I/O 2

I/O 3

Generic

Logic Block

Input Bus

I/O 107

I/O 106

I/O 105

I/O 104

Generic

Logic Block

Input Bus

I/O 14

I/O 15

I/O 16

I/O 17

I/O 93

I/O 92

I/O 91

I/O 90

Generic

Logic Block

Input Bus

I/O 18

I/O 19

I/O 20

I/O 21

Global Routing Pool

(GRP)

Generic

Logic Block

I/O 89

I/O 88

I/O 87

I/O 86

Input Bus

I/O 32

I/O 33

I/O 34

I/O 35

I/O 75

I/O 74

I/O 73

I/O 72

Generic

Logic Block

Generic

Logic Block

Input Bus

RESET

Input Bus

I/O 54

I/O 55

I/O 56

I/O 57

CLK 0

CLK 1

1CLK 2

1CLK 3

I/O 36

I/O 37

I/O 38

I/O 39

1. CLK2, CLK3 and TOE signals are shared with I/O signals. Use the table below to determine

which I/O is shared by package type.

Package Type

100 TQFP

128 TQFP

256 fpBGA

272 BGA

I/O 50

I/O 51

I/O 52

I/O 53

1/O 44 / CLK2

I/O 59 / CLK2

I/O 119 / CLK2

Multplexed Signals

I/O 49 / CLK 3

I/O 65 / CLK3

I/O 131 / CLK3

I/O 68

I/O 69

I/O 70

I/O 71

I/O 0 / TOE

Specifications

ispLSI 5256VE

ispLSI 5000VE Description (Continued)

The 32 registered macrocells in the GLB are driven by the

32 outputs from the PTSA or the PTSA bypass. Each

macrocell contains a programmable XOR gate, a pro-

grammable register/latch and the necessary clocks and

control logic to allow combinatorial or registered opera-

tion. The macrocells each have two outputs, combinatorial

and registered. This dual output capability from the

macrocell allows efficient use of the hardware resources.

One output can be a registered function for example,

while the other output can be an unrelated combinatorial

function. A direct register input from the I/O pad facili-

tates efficient use of this feature to construct high-speed

input registers.

Macrocell registers can be clocked from one of several

global or product term clocks available on the device. A

global and product term clock enable is also available to

each register, eliminating the need to gate the clock to the

macrocell registers. Reset for the macrocell register is

provided from the global signal, its polarity is user-

selectable. The macrocell register can be programmed to

operate as a D-type register or a D-type latch.

The 32 outputs from the GLB can drive both the Global

Routing Pool and the device I/O cells. The Global Routing

Pool contains one input from each macrocell output and

one input from each I/O pin.

The input buffer threshold has programmable TTL/3.3V/

2.5V compatible levels. The output driver can source

4mA and sink 8mA in 3.3V mode. The output drivers have

a separate VCCIO reference input which is independent

of the main VCC supply for the device. This feature allows

individual output drivers to drive either 3.3V (from the

device VCC) or 2.5V (from the VCCIO pin) output levels

while the device logic and the output current drive are

powered from device supply (VCC). The output drivers

also provide individually programmable edge rates and

open drain capability. A programmable pullup resistor is

provided to tie off unused inputs. Additionally, a program-

mable bus-hold latch is available to hold tristate outputs

in their last valid state until the bus is driven again by

some device.

Table 1. ispLSI 5000VE Family

Package Type

Device

ispLSI 5128VE

ispLSI 5256VE

ispLSI 5384VE

ispLSI 5512VE

GLBs

Macrocells 100 TQFP

128

256

384

512

—

72 I/O

—

128 TQFP

96 I/O

—

256 fpBGA

—

144 I/O

192 I/O

272 BGA

—

144 I/O

192 I/O

388 fpBGA

—

256 I/O

388 BGA

—

256 I/O

The ispLSI 5000VE Family features 3.3V, non-volatile in-

system programmability for both the logic and the

interconnect structures, providing the means to develop

truly reconfigurable systems. Programming is achieved

through the industry standard IEEE 1149.1-compliant

Boundary Scan interface. Boundary Scan test is also

supported through the same interface.

An enhanced, multiple cell security scheme is provided

that prevents reading of the JEDEC programming file

when secured. After the device has been secured using

this mechanism, the only way to clear the security is to

execute a bulk-erase instruction.

ispLSI 5000VE Family Members

The ispLSI 5000VE Family ranges from 128 macrocells

to 512 macrocells and operates from a 3.3V power

supply. All family members will be available with multiple

package options. The ispLSI 5000VE Family device

matrix showing the various bondout options is shown in

the table below.

The interconnect structure (GRP) is very similar to Lattice's

existing ispLSI 1000, 2000 and 3000 families, but with an

enhanced interconnect structure for optimal pin locking

and logic routing. This eliminates the need for registered

I/O cells or an Output Routing Pool.

The ispLSI 5000VE encompasses the innovative fea-

tures of the ispLSI 5000VA family with several

enhancements. The macrocell is optimized and the T-

type flip flop option is removed. To improve the efficiency

of design fits, the Product Term Reset Logic is simplified

and the polarity option as well as the Global Preset

function are removed. The programmable output-delay

feature (skew option) is also removed. As a result, the

ispLSI 5000VE is not JEDEC compatible with the ispLSI

5000VA. ispLSI 5000VA and 5000VE pinouts may differ

in the same package, however all programming and

power/ground pins are located in the same locations.

Specifications

ispLSI 5256VE

Figure 2. ispLSI 5256VE Block Diagram (144 I/O Version)

CLK2

I/O

GLB4

GLB3

I/O

160

CLK3

I/O

GLB5

GLB2

I/O

160

I/O

GLB6

GLB1

I/O

160

I/O

GLB7

GLB0

I/O

IO0/TOE

400

160

CLK0

CLK1

GOE0

GOE1

RESET

Specifications

ispLSI 5256VE

Figure 3. ispLSI 5000VE Generic Logic Block (GLB)

From GRP

0 1 2

66 67

Global PTOE Bus

PTSA

PT 0

PT 1

PT 2

PT 3

PT 4

PTOE

PT Clock

PT Reset

PT Preset

Shared PT Clock

Shared PT Reset

Global PTOE 0 ... 3

To GRP

PTSA bypass

Macrocell 0

From PTSA

To I/O Pad

PT 9

PT 8

PT 7

PT 6

PT 5

Macrocell 1

From PTSA

PTSA bypass

To I/O Pad

PTOE

PT Clock

PT Reset

PT Preset

Shared PT Clock

Shared PT Reset

Global PTOE 0 ... 3

To GRP

PT 79

PT 78

PT 77

PT 76

PT 75

Macrocell 15

From PTSA

PTSA bypass

To I/O Pad

PTOE

PT Clock

PT Reset

PT Preset

Shared PT Clock

Shared PT Reset

Global PTOE 0 ... 3

To GRP

PT 159

PT 158

PT 157

PT 156

PT 155

Macrocell 31

From PTSA

PTSA bypass

To I/O Pad

PTOE

PT Clock

PT Reset

PT Preset

PT 160

PT 161

PT 162

Shared PT Clock

Shared PT Reset

Global PTOE 0 ... 3

To GRP