The CD4042BM/CD4042BC quad clocked ``D'' latch is amonolithic complementary MOS (CMOS) integrated circuitconstructed with P- and N-channel enhancement modetransistors. The outputs Q and Q either latch or follow thedata input depending on the clock level which is programmedby the polarity input. For polarity e 0; the informationpresent at the data input is transferred to Q and Qduring 0 clock level; and for polarity e 1, the transfer occursduring the 1 clock level. When a clock transition occurs(positive for polarity e 0 and negative for polarity e 1), theinformation present at the input during the clock transition isretained at the outputs until an opposite clock transition occurs.